linux-kernel - Re: [PATCH v3 net-next 12/14] dt-bindings: net: dsa: ocelot: add ocelot-ext documentation

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20221007223824.xf7aga3rs74fmcup@skbuf>
Date:   Sat, 8 Oct 2022 01:38:24 +0300
From:   Vladimir Oltean <olteanv@...il.com>
To:     Colin Foster <colin.foster@...advantage.com>
Cc:     linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, netdev@...r.kernel.org,
        Russell King <linux@...linux.org.uk>,
        Linus Walleij <linus.walleij@...aro.org>,
        UNGLinuxDriver@...rochip.com,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Claudiu Manoil <claudiu.manoil@....com>,
        Lee Jones <lee@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Eric Dumazet <edumazet@...gle.com>,
        "David S. Miller" <davem@...emloft.net>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Andrew Lunn <andrew@...n.ch>
Subject: Re: [PATCH v3 net-next 12/14] dt-bindings: net: dsa: ocelot: add
 ocelot-ext documentation

On Fri, Oct 07, 2022 at 01:44:10PM -0700, Colin Foster wrote:
> With regards to the interrupts - I don't really have a concept of how
> those will work, since there isn't a processor for those lines to
> interrupt. So while there is this for the 7514:
> 
> interrupts = <18 21 16>;
> interrupt-names = "ptp_rdy", "xtr", "fdma";
> 
> it seems like there isn't anything to add there.
> 
> That is, unless there's something deeper that is going on that I don't
> fully understand yet. It wouldn't be the first time and, realistically,
> won't be the last. I'll copy the 7514 for now, as I plan to send out an
> RFC shortly with all these updates.

I was under the impression that the interrupt controller could be
configured to route the interrupts to external destinations EXT_DST0 or
EXT_DST1, which have the indices 2 and 3, respectively, in the DST_INTR_*
set of registers of the ICPU_CFG:INTR block. I could be wrong, though,
maybe this is just for PCIe, I never looked at the pinout of this chip
to study whether it's possible to use these as I expect, but normally
for things like PTP TX timestamping, you'd expect that the switch
notifies the external host when a packet has been timestamped and that
timestamp is available in the FIFO. The interrupts out of this switch
could also be useful for the PHY state machine, to disable polling.

Although in the general sense I agree with you, it's better not to add
anything than to add something and be wrong about it. This is where the
limitations start showing for the idea that "device tree describes
hardware, which is independent of software implementation". It's all too
easy to say this when you have an implementation already written.
Anyway.  DT doesn't describe hardware, but what software wants to
understand of it, and that makes it inseparable to some degree from
software implementation.