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Date: Sun, 9 Oct 2022 02:54:15 +0800 From: Hal Feng <hal.feng@...ux.starfivetech.com> To: Ben Dooks <ben.dooks@...ethink.co.uk> Cc: Conor Dooley <conor@...nel.org>, linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Daniel Lezcano <daniel.lezcano@...aro.org>, Thomas Gleixner <tglx@...utronix.de>, Marc Zyngier <maz@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, Stephen Boyd <sboyd@...nel.org>, Michael Turquette <mturquette@...libre.com>, Linus Walleij <linus.walleij@...aro.org>, Emil Renner Berthing <kernel@...il.dk>, linux-kernel@...r.kernel.org Subject: Re: [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs On Mon, 3 Oct 2022 10:26:44 +0100, Ben Dooks wrote: > On 29/09/2022 16:33, Conor Dooley wrote: > > On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote: > >> From: Emil Renner Berthing <kernel@...il.dk> > >> > >> This cache controller is also used on the StarFive JH7100 and JH7110 > >> SoCs. > > > > Ditto this patch, hopefully [0] will have landed as 6.1 material > > before you get around to an actual v2. > > > > Thanks, > > Conor > > > > 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/ > > Also, the l2 cache is being proprely named the ccache (composable cache) > as it is not necessarily an L2 cache. > Thanks for reminding. I will modify the code, based on the patches from Zong Li. I hope his patch series will be merged as soon as possible. Best regards, Hal
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