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Message-Id: <20221011145312.1624341-1-sashal@kernel.org>
Date: Tue, 11 Oct 2022 10:52:56 -0400
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Rajendra Nayak <quic_rjendra@...cinc.com>,
Sibi Sankar <quic_sibis@...cinc.com>,
Steev Klimaszewski <steev@...i.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Sasha Levin <sashal@...nel.org>, agross@...nel.org,
robh+dt@...nel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org
Subject: [PATCH AUTOSEL 5.10 01/17] arm64: dts: qcom: sdm845: narrow LLCC address space
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ]
The Last Level Cache Controller (LLCC) device does not need to access
entire LLCC address space. Currently driver uses only hardware info and
status registers which both reside in LLCC0_COMMON range (offset
0x30000, size 0x1000). Narrow the address space to allow binding other
drivers to rest of LLCC address space.
Cc: Rajendra Nayak <quic_rjendra@...cinc.com>
Cc: Sibi Sankar <quic_sibis@...cinc.com>
Reported-by: Steev Klimaszewski <steev@...i.org>
Suggested-by: Sibi Sankar <quic_sibis@...cinc.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Tested-by: Steev Klimaszewski <steev@...i.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 9beb3c34fcdb..068fad00e615 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1796,7 +1796,7 @@ uart15: serial@...000 {
system-cache-controller@...0000 {
compatible = "qcom,sdm845-llcc";
- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
+ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.35.1
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