linux-kernel - Re: [RFC PATCH 0/2] RZ/G2UL separate out SoC specific parts

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CA+V-a8sfhHeFa=NAUvZH+DDUjRbdFoCqr4itiYHzxv_jSY9HWg@mail.gmail.com>
Date:   Wed, 12 Oct 2022 20:00:11 +0100
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Samuel Holland <samuel@...lland.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        DT <devicetree@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [RFC PATCH 0/2] RZ/G2UL separate out SoC specific parts

Hi Krzysztof,

On Wed, Oct 12, 2022 at 4:38 PM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 10/10/2022 05:41, Lad, Prabhakar wrote:
> > Hi Rob, Krzysztof,
> >
> > On Thu, Sep 29, 2022 at 6:24 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> >>
> >> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >>
> >> Hi All,
> >>
> >> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
> >> so that this can be shared with the RZ/Five SoC.
> >>
> >> Implementation is based on the discussion [0] where I have used option#2.
> >>
> >> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
> >> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
> >> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
> >> (r9a07g043F.dtsi)
> >>
> >> Sending this as an RFC to get some feedback.
> >>
> >> r9a07g043f.dtsi will look something like below:
> >>
> >> #include <dt-bindings/interrupt-controller/irq.h>
> >>
> >> #define SOC_PERIPHERAL_IRQ_NUMBER(nr)   (nr + 32)
> >> #define SOC_PERIPHERAL_IRQ(nr, na)      SOC_PERIPHERAL_IRQ_NUMBER(nr) na
> >>
> >> #include <arm64/renesas/r9a07g043.dtsi>
> >>
> >> / {
> >>    ...
> >>    ...
> >> };
> >>
> >> Although patch#2 can be merged into patch#1 just wanted to keep them separated
> >> for easier review.
> >>
> >> [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/
> >>
> >> Cheers,
> >> Prabhakar
> >>
> >> Lad Prabhakar (2):
> >>   arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
> >>     to specify interrupt property
> >
> > Can either of you please review patch #1.
> >
>
> Why? This is a DTS patch, isn't it? You should CC rather platform
> maintainers, architecture maintainers and SoC folks (the latter you
> missed for sure). You missed them, so please resend.
>
Mainly because we are using the SOC_PERIPHERAL_IRQ() macro while
specifying the interrupts property and just wanted to make sure the DT
maintainers are OK with that.

Sure I'll resend the patches CC'ing ARCH maintainers after v6.1-rc1.

Cheers,
Prabhakar