linux-kernel - [PATCH V3 09/21] PCI: tegra194: Calibrate P2U for endpoint mode

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20221013183854.21087-10-vidyas@nvidia.com>
Date:   Fri, 14 Oct 2022 00:08:42 +0530
From:   Vidya Sagar <vidyas@...dia.com>
To:     <lpieralisi@...nel.org>, <robh@...nel.org>, <kw@...ux.com>,
        <bhelgaas@...gle.com>, <thierry.reding@...il.com>,
        <jonathanh@...dia.com>, <kishon@...com>, <vkoul@...nel.org>,
        <mani@...nel.org>, <Sergey.Semin@...kalelectronics.ru>,
        <ffclaire1224@...il.com>
CC:     <linux-pci@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
        <kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>,
        <sagar.tv@...il.com>
Subject: [PATCH V3 09/21] PCI: tegra194: Calibrate P2U for endpoint mode

Calibrate P2U for endpoint controller to request UPHY PLL rate change to
Gen1 during initialization. This helps to reset stale PLL state from the
previous bad link state.

Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
V3:
* Reworded the commit message

V2:
* None

 drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index dff38f73d9a7..910dc6c2154e 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1130,6 +1130,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
 		ret = phy_power_on(pcie->phys[i]);
 		if (ret < 0)
 			goto phy_exit;
+
+		if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+			phy_calibrate(pcie->phys[i]);
 	}
 
 	return 0;
-- 
2.17.1