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Message-ID: <20221013183854.21087-13-vidyas@nvidia.com>
Date: Fri, 14 Oct 2022 00:08:45 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <lpieralisi@...nel.org>, <robh@...nel.org>, <kw@...ux.com>,
<bhelgaas@...gle.com>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <kishon@...com>, <vkoul@...nel.org>,
<mani@...nel.org>, <Sergey.Semin@...kalelectronics.ru>,
<ffclaire1224@...il.com>
CC: <linux-pci@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
<kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>,
<sagar.tv@...il.com>
Subject: [PATCH V3 12/21] PCI: tegra194: Enable DMA interrupt
Enable DMA interrupt to support Tegra PCIe DMA in both Root port and
Endpoint modes.
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
V3:
* This is a new patch in this series
drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 786e5d5f43b9..a1c3481585c9 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -94,6 +94,7 @@
#define APPL_INTR_EN_L1_8_0 0x44
#define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2)
#define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3)
+#define APPL_INTR_EN_L1_8_EDMA_INT_EN BIT(6)
#define APPL_INTR_EN_L1_8_INTX_EN BIT(11)
#define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15)
@@ -552,6 +553,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
spurious = 0;
}
+ if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {
+ status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
+ /* Interrupt is handled by dma driver, don't treat it as spurious */
+ if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK)
+ spurious = 0;
+ }
+
if (spurious) {
dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
status_l0);
@@ -781,6 +789,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp)
val |= APPL_INTR_EN_L1_8_INTX_EN;
val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
+ val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
if (IS_ENABLED(CONFIG_PCIEAER))
val |= APPL_INTR_EN_L1_8_AER_INT_EN;
appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
@@ -1927,6 +1936,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
+ val |= APPL_INTR_EN_L0_0_INT_INT_EN;
appl_writel(pcie, val, APPL_INTR_EN_L0_0);
val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
@@ -1934,6 +1944,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
+ val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
+ val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
+ appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
+
reset_control_deassert(pcie->core_rst);
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
--
2.17.1
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