| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <202210140359.vQTHtEBO-lkp@intel.com>
Date: Fri, 14 Oct 2022 03:22:35 +0800
From: kernel test robot <lkp@...el.com>
To: Masahiro Yamada <masahiroy@...nel.org>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: [masahiroy:kbuild 8/8] arch/arm/kernel/entry-armv.S:485:5: warning:
"CONFIG_ARM_THUMB" is not defined, evaluates to 0
Hi Masahiro,
First bad commit (maybe != root cause):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git kbuild
head: 0a7606a9832ab375a38425a659bda13712ca89ae
commit: 0a7606a9832ab375a38425a659bda13712ca89ae [8/8] kbuild: move -Wundef from KBUILD_CFLAGS to KBUILD_CPPFLAGS
config: arm-randconfig-r032-20221012
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git/commit/?id=0a7606a9832ab375a38425a659bda13712ca89ae
git remote add masahiroy https://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
git fetch --no-tags masahiroy kbuild
git checkout 0a7606a9832ab375a38425a659bda13712ca89ae
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash arch/arm/kernel/ drivers/perf/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> arch/arm/kernel/entry-armv.S:485:5: warning: "CONFIG_ARM_THUMB" is not defined, evaluates to 0 [-Wundef]
485 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
| ^~~~~~~~~~~~~~~~
arch/arm/kernel/entry-armv.S:544:5: warning: "CONFIG_ARM_THUMB" is not defined, evaluates to 0 [-Wundef]
544 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
| ^~~~~~~~~~~~~~~~
vim +/CONFIG_ARM_THUMB +485 arch/arm/kernel/entry-armv.S
^1da177e4c3f41 Linus Torvalds 2005-04-16 442
^1da177e4c3f41 Linus Torvalds 2005-04-16 443 .ltorg
^1da177e4c3f41 Linus Torvalds 2005-04-16 444
^1da177e4c3f41 Linus Torvalds 2005-04-16 445 .align 5
^1da177e4c3f41 Linus Torvalds 2005-04-16 446 __und_usr:
2190fed67ba6f3 Russell King 2015-08-20 447 usr_entry uaccess=0
bc089602d206b2 Russell King 2011-06-25 448
b059bdc3932169 Russell King 2011-06-25 449 mov r2, r4
b059bdc3932169 Russell King 2011-06-25 450 mov r3, r5
^1da177e4c3f41 Linus Torvalds 2005-04-16 451
15ac49b65024f5 Russell King 2012-07-30 452 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
15ac49b65024f5 Russell King 2012-07-30 453 @ faulting instruction depending on Thumb mode.
15ac49b65024f5 Russell King 2012-07-30 454 @ r3 = regs->ARM_cpsr
^1da177e4c3f41 Linus Torvalds 2005-04-16 455 @
15ac49b65024f5 Russell King 2012-07-30 456 @ The emulation code returns using r9 if it has emulated the
15ac49b65024f5 Russell King 2012-07-30 457 @ instruction, or the more conventional lr if we are to treat
15ac49b65024f5 Russell King 2012-07-30 458 @ this as a real undefined instruction
^1da177e4c3f41 Linus Torvalds 2005-04-16 459 @
14327c662822e5 Russell King 2015-04-21 460 badr r9, ret_from_exception
15ac49b65024f5 Russell King 2012-07-30 461
1417a6b8dc4db7 Catalin Marinas 2014-04-22 462 @ IRQs must be enabled before attempting to read the instruction from
1417a6b8dc4db7 Catalin Marinas 2014-04-22 463 @ user space since that could cause a page/translation fault if the
1417a6b8dc4db7 Catalin Marinas 2014-04-22 464 @ page table was modified by another CPU.
1417a6b8dc4db7 Catalin Marinas 2014-04-22 465 enable_irq
1417a6b8dc4db7 Catalin Marinas 2014-04-22 466
cb170a45d69b57 Paul Brook 2008-04-18 467 tst r3, #PSR_T_BIT @ Thumb mode?
15ac49b65024f5 Russell King 2012-07-30 468 bne __und_usr_thumb
15ac49b65024f5 Russell King 2012-07-30 469 sub r4, r2, #4 @ ARM instr at LR - 4
15ac49b65024f5 Russell King 2012-07-30 470 1: ldrt r0, [r4]
457c2403c513c7 Ben Dooks 2013-02-12 471 ARM_BE8(rev r0, r0) @ little endian instruction
457c2403c513c7 Ben Dooks 2013-02-12 472
2190fed67ba6f3 Russell King 2015-08-20 473 uaccess_disable ip
2190fed67ba6f3 Russell King 2015-08-20 474
15ac49b65024f5 Russell King 2012-07-30 475 @ r0 = 32-bit ARM instruction which caused the exception
15ac49b65024f5 Russell King 2012-07-30 476 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
15ac49b65024f5 Russell King 2012-07-30 477 @ r4 = PC value for the faulting instruction
15ac49b65024f5 Russell King 2012-07-30 478 @ lr = 32-bit undefined instruction function
14327c662822e5 Russell King 2015-04-21 479 badr lr, __und_usr_fault_32
15ac49b65024f5 Russell King 2012-07-30 480 b call_fpe
15ac49b65024f5 Russell King 2012-07-30 481
15ac49b65024f5 Russell King 2012-07-30 482 __und_usr_thumb:
cb170a45d69b57 Paul Brook 2008-04-18 483 @ Thumb instruction
15ac49b65024f5 Russell King 2012-07-30 484 sub r4, r2, #2 @ First half of thumb instr at LR - 2
ef4c53687e0adf Dave Martin 2011-08-19 @485 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
ef4c53687e0adf Dave Martin 2011-08-19 486 /*
ef4c53687e0adf Dave Martin 2011-08-19 487 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
ef4c53687e0adf Dave Martin 2011-08-19 488 * can never be supported in a single kernel, this code is not applicable at
ef4c53687e0adf Dave Martin 2011-08-19 489 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
ef4c53687e0adf Dave Martin 2011-08-19 490 * made about .arch directives.
ef4c53687e0adf Dave Martin 2011-08-19 491 */
ef4c53687e0adf Dave Martin 2011-08-19 492 #if __LINUX_ARM_ARCH__ < 7
ef4c53687e0adf Dave Martin 2011-08-19 493 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
508074607c7b95 Ard Biesheuvel 2022-04-20 494 ldr_va r5, cpu_architecture
ef4c53687e0adf Dave Martin 2011-08-19 495 cmp r5, #CPU_ARCH_ARMv7
15ac49b65024f5 Russell King 2012-07-30 496 blo __und_usr_fault_16 @ 16bit undefined instruction
ef4c53687e0adf Dave Martin 2011-08-19 497 /*
ef4c53687e0adf Dave Martin 2011-08-19 498 * The following code won't get run unless the running CPU really is v7, so
ef4c53687e0adf Dave Martin 2011-08-19 499 * coding round the lack of ldrht on older arches is pointless. Temporarily
ef4c53687e0adf Dave Martin 2011-08-19 500 * override the assembler target arch with the minimum required instead:
ef4c53687e0adf Dave Martin 2011-08-19 501 */
ef4c53687e0adf Dave Martin 2011-08-19 502 .arch armv6t2
ef4c53687e0adf Dave Martin 2011-08-19 503 #endif
15ac49b65024f5 Russell King 2012-07-30 504 2: ldrht r5, [r4]
f8fe23ec4e89b5 Victor Kamensky 2014-01-21 505 ARM_BE8(rev16 r5, r5) @ little endian instruction
85519189df91c8 Dave Martin 2011-08-19 506 cmp r5, #0xe800 @ 32bit instruction if xx != 0
2190fed67ba6f3 Russell King 2015-08-20 507 blo __und_usr_fault_16_pan @ 16bit undefined instruction
15ac49b65024f5 Russell King 2012-07-30 508 3: ldrht r0, [r2]
f8fe23ec4e89b5 Victor Kamensky 2014-01-21 509 ARM_BE8(rev16 r0, r0) @ little endian instruction
2190fed67ba6f3 Russell King 2015-08-20 510 uaccess_disable ip
cb170a45d69b57 Paul Brook 2008-04-18 511 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
15ac49b65024f5 Russell King 2012-07-30 512 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
cb170a45d69b57 Paul Brook 2008-04-18 513 orr r0, r0, r5, lsl #16
14327c662822e5 Russell King 2015-04-21 514 badr lr, __und_usr_fault_32
15ac49b65024f5 Russell King 2012-07-30 515 @ r0 = the two 16-bit Thumb instructions which caused the exception
15ac49b65024f5 Russell King 2012-07-30 516 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
15ac49b65024f5 Russell King 2012-07-30 517 @ r4 = PC value for the first 16-bit Thumb instruction
15ac49b65024f5 Russell King 2012-07-30 518 @ lr = 32bit undefined instruction function
ef4c53687e0adf Dave Martin 2011-08-19 519
:::::: The code at line 485 was first introduced by commit
:::::: ef4c53687e0adf5409896c4fa688b15f8d4dc0c0 ARM: 7031/1: entry: Fix Thumb-2 undef handling for multi-CPU kernels
:::::: TO: Dave Martin <dave.martin@...aro.org>
:::::: CC: Russell King <rmk+kernel@....linux.org.uk>
--
0-DAY CI Kernel Test Service
https://01.org/lkp
View attachment "config" of type "text/plain" (191298 bytes)
Powered by blists - more mailing lists