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Message-ID: <69F8F5CF-D939-4AC1-A691-06DD15746F1C@zytor.com>
Date: Thu, 13 Oct 2022 13:05:09 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: "Li, Xin3" <xin3.li@...el.com>,
"Bae, Chang Seok" <chang.seok.bae@...el.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"x86@...nel.org" <x86@...nel.org>
CC: "tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"peterz@...radead.org" <peterz@...radead.org>
Subject: RE: [PATCH v2 1/6] x86/cpufeature: add cpu feature bit for LKGS
On October 13, 2022 12:35:23 PM PDT, "Li, Xin3" <xin3.li@...el.com> wrote:
>
>> > diff --git a/arch/x86/include/asm/cpufeatures.h
>> > b/arch/x86/include/asm/cpufeatures.h
>> > index ef4775c6db01..459fb0c21dd4 100644
>> > --- a/arch/x86/include/asm/cpufeatures.h
>> > +++ b/arch/x86/include/asm/cpufeatures.h
>> > @@ -308,6 +308,7 @@
>> > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
>> > #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI
>> instructions */
>> > #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512
>> BFLOAT16 instructions */
>> > +#define X86_FEATURE_LKGS (12*32+ 18) /* Load "kernel"
>> (userspace) gs */
>>
>> The spec says [1]:
>> "Execution of LKGS causes an invalid-opcode exception (#UD) if CPL >
>> 0."
>>
>> Perhaps userspace has no interest in this. Then, we can add "" not to show
>> "lkgs" in /proc/cpuinfo:
>> +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel"
>> (userspace) gs */
>
>Good point!
>
>>
>> Thanks,
>> Chang
>>
>> [1] https://cdrdv2.intel.com/v1/dl/getContent/678938
>
It would be useful for reviewers to mention that this is was a policy change on the maintainers' part. This is totally valid, of course, but making it explicit would perhaps help reduce potential confusion.
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