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Message-ID: <Y0fPOjlLrxj0mm2R@black.fi.intel.com>
Date: Thu, 13 Oct 2022 11:41:30 +0300
From: Mika Westerberg <mika.westerberg@...ux.intel.com>
To: Mauro Lima <mauro.lima@...ypsium.com>
Cc: broonie@...nel.org, linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] spi: intel: Fix the offset to get the 64K erase opcode
On Wed, Oct 12, 2022 at 12:21:35PM -0300, Mauro Lima wrote:
> According to documentation, the 64K erase opcode is located in VSCC
> range [16:23] instead of [8:15].
> Use the proper value to shift the mask over the correct range.
>
> Signed-off-by: Mauro Lima <mauro.lima@...ypsium.com>
Reviewed-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
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