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Message-ID: <DM6PR12MB30824E232253ED0355CA776DE8249@DM6PR12MB3082.namprd12.prod.outlook.com>
Date: Fri, 14 Oct 2022 04:51:51 +0000
From: "Gupta, Nipun" <Nipun.Gupta@....com>
To: "Gupta, Nipun" <Nipun.Gupta@....com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
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CC: "okaya@...nel.org" <okaya@...nel.org>,
"Anand, Harpreet" <harpreet.anand@....com>,
"Agarwal, Nikhil" <nikhil.agarwal@....com>,
"Simek, Michal" <michal.simek@....com>,
"Radovanovic, Aleksandar" <aleksandar.radovanovic@....com>,
"git (AMD-Xilinx)" <git@....com>
Subject: RE: [RFC PATCH v4 3/8] iommu/arm-smmu-v3: support ops registration
for CDX bus
[AMD Official Use Only - General]
This patch will be rebased on top of https://lore.kernel.org/linux-iommu/cover.1660572783.git.robin.murphy@arm.com/T/#t
in next respin.
Regards,
Nipun
> -----Original Message-----
> From: Nipun Gupta <nipun.gupta@....com>
> Sent: Friday, October 14, 2022 10:11 AM
> To: robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> gregkh@...uxfoundation.org; rafael@...nel.org; eric.auger@...hat.com;
> alex.williamson@...hat.com; cohuck@...hat.com; Gupta, Puneet (DCG-ENG)
> <puneet.gupta@....com>; song.bao.hua@...ilicon.com;
> mchehab+huawei@...nel.org; maz@...nel.org; f.fainelli@...il.com;
> jeffrey.l.hugo@...il.com; saravanak@...gle.com; Michael.Srba@...nam.cz;
> mani@...nel.org; yishaih@...dia.com; jgg@...pe.ca; jgg@...dia.com;
> robin.murphy@....com; will@...nel.org; joro@...tes.org;
> masahiroy@...nel.org; ndesaulniers@...gle.com; linux-arm-
> kernel@...ts.infradead.org; linux-kbuild@...r.kernel.org; linux-
> kernel@...r.kernel.org; devicetree@...r.kernel.org; kvm@...r.kernel.org
> Cc: okaya@...nel.org; Anand, Harpreet <harpreet.anand@....com>; Agarwal,
> Nikhil <nikhil.agarwal@....com>; Simek, Michal <michal.simek@....com>;
> Radovanovic, Aleksandar <aleksandar.radovanovic@....com>; git (AMD-Xilinx)
> <git@....com>; Gupta, Nipun <Nipun.Gupta@....com>
> Subject: [RFC PATCH v4 3/8] iommu/arm-smmu-v3: support ops registration for
> CDX bus
>
> With new CDX bus supported for AMD FPGA devices on ARM
> platform, the bus requires registration for the SMMU v3
> driver.
>
> Signed-off-by: Nipun Gupta <nipun.gupta@....com>
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index d32b02336411..8ec9f2baf12d 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -29,6 +29,7 @@
> #include <linux/platform_device.h>
>
> #include <linux/amba/bus.h>
> +#include <linux/cdx/cdx_bus.h>
>
> #include "arm-smmu-v3.h"
> #include "../../iommu-sva-lib.h"
> @@ -3690,16 +3691,27 @@ static int arm_smmu_set_bus_ops(struct
> iommu_ops *ops)
> if (err)
> goto err_reset_pci_ops;
> }
> +#endif
> +#ifdef CONFIG_CDX_BUS
> + if (cdx_bus_type.iommu_ops != ops) {
> + err = bus_set_iommu(&cdx_bus_type, ops);
> + if (err)
> + goto err_reset_amba_ops;
> + }
> #endif
> if (platform_bus_type.iommu_ops != ops) {
> err = bus_set_iommu(&platform_bus_type, ops);
> if (err)
> - goto err_reset_amba_ops;
> + goto err_reset_cdx_ops;
> }
>
> return 0;
>
> -err_reset_amba_ops:
> +err_reset_cdx_ops:
> +#ifdef CONFIG_CDX_BUS
> + bus_set_iommu(&cdx_bus_type, NULL);
> +#endif
> +err_reset_amba_ops: __maybe_unused;
> #ifdef CONFIG_ARM_AMBA
> bus_set_iommu(&amba_bustype, NULL);
> #endif
> --
> 2.25.1
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