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Message-ID: <20221017192532.23825-8-afd@ti.com>
Date: Mon, 17 Oct 2022 14:25:29 -0500
From: Andrew Davis <afd@...com>
To: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: Andrew Davis <afd@...com>
Subject: [PATCH 07/10] arm64: dts: ti: k3-am64: MDIO pinmux should belong to the MDIO node
Although usually integrated as a child of an Ethernet controller, MDIO
IP has an independent pinout. This pinout should be controlled by
the MDIO node (so if it was to be disabled for instance, the pinmux
state would reflect that).
Move the MDIO pins pinmux to the MIDO nodes.
Signed-off-by: Andrew Davis <afd@...com>
---
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 6 ++++--
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 6 ++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 2dec25d90240..2319ba4f5ae3 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -425,8 +425,7 @@ &usb0 {
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
+ pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -441,6 +440,9 @@ &cpsw_port2 {
};
&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 58c71608d925..c1d634647027 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -439,8 +439,7 @@ &usb0 {
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
+ pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -455,6 +454,9 @@ &cpsw_port2 {
};
&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
--
2.37.3
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