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Message-Id: <20221017210949.1B54AC433D6@smtp.kernel.org>
Date:   Mon, 17 Oct 2022 14:09:47 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Sean Anderson <seanga2@...il.com>, linux-clk@...r.kernel.org,
        linux-mips@...r.kernel.org
Cc:     Yang Ling <gnaygnil@...il.com>, linux-kernel@...r.kernel.org,
        Kelvin Cheung <keguang.zhang@...il.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Du Huanpeng <dhu@...carrier.org>,
        Sean Anderson <seanga2@...il.com>
Subject: Re: [RESEND PATCH] clk: ls1c: Fix PLL rate calculation

Quoting Sean Anderson (2022-08-22 20:34:14)
> While reviewing Dhu's patch adding ls1c300 clock support to U-Boot [1], I
> noticed the following calculation, which is copied from
> drivers/clk/loongson1/clk-loongson1c.c:
> 

Nobody has provided a review for this patch. If it is still important,
please resend. Thanks.

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