linux-kernel - Re: [PATCH v4 4/4] clk: mxl: Fix a clk entry by adding relevant flags

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Message-Id: <20221017222909.A1D51C433D7@smtp.kernel.org>
Date:   Mon, 17 Oct 2022 15:29:07 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Rahul Tanwar <rtanwar@...linear.com>, linux-clk@...r.kernel.org,
        mturquette@...libre.com, yzhu@...linear.com
Cc:     linux-kernel@...r.kernel.org, linux-lgm-soc@...linear.com,
        Rahul Tanwar <rtanwar@...linear.com>
Subject: Re: [PATCH v4 4/4] clk: mxl: Fix a clk entry by adding relevant flags

Quoting Rahul Tanwar (2022-10-12 23:48:33)
> One of the clock entry "dcl" clk has some HW limitations. One is that
> its rate can only by changed by changing its parent clk's rate & two
> is that HW does not support enable/disable for this clk.
> 
> Handle above two limitations by adding relevant flags. Add standard
> flag CLK_SET_RATE_PARENT to handle rate change and add driver internal
> flag DIV_CLK_NO_MASK to handle enable/disable.
> 
> Fixes: d058fd9e8984c ("clk: intel: Add CGU clock driver for a new SoC")
> Reviewed-by: Yi xin Zhu <yzhu@...linear.com>
> Signed-off-by: Rahul Tanwar <rtanwar@...linear.com>
> ---

Applied to clk-next