linux-kernel - [sean-jc:x86/rework_kvm_init 39/39] arch/riscv/kvm/main.c:23:5: warning: no previous prototype for 'kvm_arch_hardware

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Date:   Mon, 17 Oct 2022 16:55:40 +0800
From:   kernel test robot <lkp@...el.com>
To:     Sean Christopherson <seanjc@...gle.com>
Cc:     kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: [sean-jc:x86/rework_kvm_init 39/39] arch/riscv/kvm/main.c:23:5:
 warning: no previous prototype for 'kvm_arch_hardware_enable'

tree:   https://github.com/sean-jc/linux x86/rework_kvm_init
head:   419450c654fa58b3708d7b15cb6b20dfb80b472a
commit: 419450c654fa58b3708d7b15cb6b20dfb80b472a [39/39] KVM: Allow architectures to opt out of generic hardware enabling
config: riscv-randconfig-r034-20221017
compiler: riscv32-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/sean-jc/linux/commit/419450c654fa58b3708d7b15cb6b20dfb80b472a
        git remote add sean-jc https://github.com/sean-jc/linux
        git fetch --no-tags sean-jc x86/rework_kvm_init
        git checkout 419450c654fa58b3708d7b15cb6b20dfb80b472a
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash arch/riscv/kvm/ virt/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>

All warnings (new ones prefixed by >>):

>> arch/riscv/kvm/main.c:23:5: warning: no previous prototype for 'kvm_arch_hardware_enable' [-Wmissing-prototypes]
      23 | int kvm_arch_hardware_enable(void)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/main.c:49:6: warning: no previous prototype for 'kvm_arch_hardware_disable' [-Wmissing-prototypes]
      49 | void kvm_arch_hardware_disable(void)
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~


vim +/kvm_arch_hardware_enable +23 arch/riscv/kvm/main.c

99cdc6c18c2d815 Anup Patel   2021-09-27  22  
99cdc6c18c2d815 Anup Patel   2021-09-27 @23  int kvm_arch_hardware_enable(void)
99cdc6c18c2d815 Anup Patel   2021-09-27  24  {
99cdc6c18c2d815 Anup Patel   2021-09-27  25  	unsigned long hideleg, hedeleg;
99cdc6c18c2d815 Anup Patel   2021-09-27  26  
99cdc6c18c2d815 Anup Patel   2021-09-27  27  	hedeleg = 0;
99cdc6c18c2d815 Anup Patel   2021-09-27  28  	hedeleg |= (1UL << EXC_INST_MISALIGNED);
99cdc6c18c2d815 Anup Patel   2021-09-27  29  	hedeleg |= (1UL << EXC_BREAKPOINT);
99cdc6c18c2d815 Anup Patel   2021-09-27  30  	hedeleg |= (1UL << EXC_SYSCALL);
99cdc6c18c2d815 Anup Patel   2021-09-27  31  	hedeleg |= (1UL << EXC_INST_PAGE_FAULT);
99cdc6c18c2d815 Anup Patel   2021-09-27  32  	hedeleg |= (1UL << EXC_LOAD_PAGE_FAULT);
99cdc6c18c2d815 Anup Patel   2021-09-27  33  	hedeleg |= (1UL << EXC_STORE_PAGE_FAULT);
99cdc6c18c2d815 Anup Patel   2021-09-27  34  	csr_write(CSR_HEDELEG, hedeleg);
99cdc6c18c2d815 Anup Patel   2021-09-27  35  
99cdc6c18c2d815 Anup Patel   2021-09-27  36  	hideleg = 0;
99cdc6c18c2d815 Anup Patel   2021-09-27  37  	hideleg |= (1UL << IRQ_VS_SOFT);
99cdc6c18c2d815 Anup Patel   2021-09-27  38  	hideleg |= (1UL << IRQ_VS_TIMER);
99cdc6c18c2d815 Anup Patel   2021-09-27  39  	hideleg |= (1UL << IRQ_VS_EXT);
99cdc6c18c2d815 Anup Patel   2021-09-27  40  	csr_write(CSR_HIDELEG, hideleg);
99cdc6c18c2d815 Anup Patel   2021-09-27  41  
99cdc6c18c2d815 Anup Patel   2021-09-27  42  	csr_write(CSR_HCOUNTEREN, -1UL);
99cdc6c18c2d815 Anup Patel   2021-09-27  43  
99cdc6c18c2d815 Anup Patel   2021-09-27  44  	csr_write(CSR_HVIP, 0);
99cdc6c18c2d815 Anup Patel   2021-09-27  45  
99cdc6c18c2d815 Anup Patel   2021-09-27  46  	return 0;
99cdc6c18c2d815 Anup Patel   2021-09-27  47  }
99cdc6c18c2d815 Anup Patel   2021-09-27  48  
99cdc6c18c2d815 Anup Patel   2021-09-27 @49  void kvm_arch_hardware_disable(void)
99cdc6c18c2d815 Anup Patel   2021-09-27  50  {
33e5b5746cc2336 Vincent Chen 2021-12-27  51  	/*
33e5b5746cc2336 Vincent Chen 2021-12-27  52  	 * After clearing the hideleg CSR, the host kernel will receive
33e5b5746cc2336 Vincent Chen 2021-12-27  53  	 * spurious interrupts if hvip CSR has pending interrupts and the
33e5b5746cc2336 Vincent Chen 2021-12-27  54  	 * corresponding enable bits in vsie CSR are asserted. To avoid it,
33e5b5746cc2336 Vincent Chen 2021-12-27  55  	 * hvip CSR and vsie CSR must be cleared before clearing hideleg CSR.
33e5b5746cc2336 Vincent Chen 2021-12-27  56  	 */
33e5b5746cc2336 Vincent Chen 2021-12-27  57  	csr_write(CSR_VSIE, 0);
33e5b5746cc2336 Vincent Chen 2021-12-27  58  	csr_write(CSR_HVIP, 0);
99cdc6c18c2d815 Anup Patel   2021-09-27  59  	csr_write(CSR_HEDELEG, 0);
99cdc6c18c2d815 Anup Patel   2021-09-27  60  	csr_write(CSR_HIDELEG, 0);
99cdc6c18c2d815 Anup Patel   2021-09-27  61  }
99cdc6c18c2d815 Anup Patel   2021-09-27  62  

:::::: The code at line 23 was first introduced by commit
:::::: 99cdc6c18c2d815e940e81b9b477d469bdd41788 RISC-V: Add initial skeletal KVM support

:::::: TO: Anup Patel <anup.patel@....com>
:::::: CC: Anup Patel <anup@...infault.org>

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

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