lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 18 Oct 2022 07:22:04 +0000
From:   Bough Chen <haibo.chen@....com>
To:     Brian Norris <briannorris@...omium.org>,
        Ulf Hansson <ulf.hansson@...aro.org>
CC:     Shawn Lin <shawn.lin@...k-chips.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Shawn Guo <shawnguo@...nel.org>,
        Fabio Estevam <festevam@...il.com>,
        Faiz Abbas <faiz_abbas@...com>,
        dl-linux-imx <linux-imx@....com>,
        Al Cooper <alcooperx@...il.com>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Florian Fainelli <f.fainelli@...il.com>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Thierry Reding <thierry.reding@...il.com>,
        Michal Simek <michal.simek@...inx.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Sowjanya Komatineni <skomatineni@...dia.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Broadcom internal kernel review list 
        <bcm-kernel-feedback-list@...adcom.com>
Subject: RE: [PATCH 3/5] mms: sdhci-esdhc-imx: Fix SDHCI_RESET_ALL for CQHCI

> -----Original Message-----
> From: Brian Norris <briannorris@...omium.org>
> Sent: 2022年10月18日 11:57
> To: Ulf Hansson <ulf.hansson@...aro.org>
> Cc: Shawn Lin <shawn.lin@...k-chips.com>; Adrian Hunter
> <adrian.hunter@...el.com>; Shawn Guo <shawnguo@...nel.org>; Fabio
> Estevam <festevam@...il.com>; Faiz Abbas <faiz_abbas@...com>;
> dl-linux-imx <linux-imx@....com>; Bough Chen <haibo.chen@....com>; Al
> Cooper <alcooperx@...il.com>; linux-mmc@...r.kernel.org; Pengutronix
> Kernel Team <kernel@...gutronix.de>; linux-kernel@...r.kernel.org; Florian
> Fainelli <f.fainelli@...il.com>; Sascha Hauer <s.hauer@...gutronix.de>;
> Thierry Reding <thierry.reding@...il.com>; Michal Simek
> <michal.simek@...inx.com>; Jonathan Hunter <jonathanh@...dia.com>;
> Sowjanya Komatineni <skomatineni@...dia.com>;
> linux-arm-kernel@...ts.infradead.org; Broadcom internal kernel review list
> <bcm-kernel-feedback-list@...adcom.com>; Brian Norris
> <briannorris@...omium.org>
> Subject: [PATCH 3/5] mms: sdhci-esdhc-imx: Fix SDHCI_RESET_ALL for CQHCI
> 
>  [[ NOTE: this is completely untested by the author, but included solely
>     because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix
>     SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other
>     drivers using CQHCI might benefit from a similar change, if they
>     also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same
>     bug on at least MSM, Arasan, and Intel hardware. ]]
> 
> SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't
> tracking that properly in software. When out of sync, we may trigger various
> timeouts.
> 
> It's not typical to perform resets while CQE is enabled, but this may occur in
> some suspend or error recovery scenarios.
> 
> Fixes: bb6e358169bf ("mmc: sdhci-esdhc-imx: add CMDQ support")
> Signed-off-by: Brian Norris <briannorris@...omium.org>
> ---
> 
>  drivers/mmc/host/sdhci-esdhc-imx.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 55981b0f0b10..222c83929e20 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -1288,6 +1288,13 @@ static void esdhc_set_uhs_signaling(struct
> sdhci_host *host, unsigned timing)
> 
>  static void esdhc_reset(struct sdhci_host *host, u8 mask)  {
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
> +
> +	if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)
> &&
> +	    imx_data->socdata->flags & ESDHC_FLAG_CQHCI)

I think we can remove the condition " imx_data->socdata->flags & ESDHC_FLAG_CQHCI" here.
According to code logic, host->mmc->caps2 & MMC_CAP2_CQE means it already contain imx_data->socdata->flags & ESDHC_FLAG_CQHCI

Best Regards
Haibo Chen


> +		cqhci_deactivate(host->mmc);
> +
>  	sdhci_reset(host, mask);
> 
>  	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
> --
> 2.38.0.413.g74048e4d9e-goog

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ