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Message-ID: <e58d7c6d-cf8a-017b-7e72-6ae579ce6be2@xen0n.name>
Date: Tue, 18 Oct 2022 16:09:27 +0800
From: WANG Xuerui <kernel@...0n.name>
To: David Laight <David.Laight@...LAB.COM>,
'Huacai Chen' <chenhuacai@...nel.org>
Cc: Huacai Chen <chenhuacai@...ngson.cn>,
"loongarch@...ts.linux.dev" <loongarch@...ts.linux.dev>,
Xuefeng Li <lixuefeng@...ngson.cn>,
Tiezhu Yang <yangtiezhu@...ngson.cn>,
Guo Ren <guoren@...nel.org>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2] LoongArch: Add unaligned access support
On 2022/10/18 15:48, David Laight wrote:
> From: Huacai Chen
>> Sent: 18 October 2022 08:33
> ...
>>> What about my more structured approach in another reply that avoids the
>>> huge else-if conditions? Both the terrible line wraps and codegen could
>>> be avoided.
> ...
>> OK, let me try.
>
> I suspect you can mask out some 'operand size' bits from the
> instructions - instead of checking each opcode.
Technically LoongArch instruction formats don't contain any "operand
size bit", because most current opcodes seem to be simply sequentially
allocated. While there seem to exist a certain pattern in e.g. encodings
of {LD,ST,FLD,FST}.{B,H,W,D}, I believe it's just coincidence (e.g. bits
23:22 of those instructions seem to represent "B/H/W/D"; but other
instructions clearly don't follow such a pattern, not even the
{LD,ST}.{BU,HU,WU} ones).
For now I'd personally prefer readability and maintainability over
performance, because traps are already expensive enough that
optimizations like this don't really matter.
--
WANG "xen0n" Xuerui
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