linux-kernel - Re: [PATCH 10/15] dt-bindings: phy: qcom,qmp-pcie: add sc8280xp bindings

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Message-ID: <Y050nxCaFXIgczrA@hovoldconsulting.com>
Date:   Tue, 18 Oct 2022 11:40:47 +0200
From:   Johan Hovold <johan@...nel.org>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     Johan Hovold <johan+linaro@...nel.org>,
        Vinod Koul <vkoul@...nel.org>, Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 10/15] dt-bindings: phy: qcom,qmp-pcie: add sc8280xp
 bindings

On Mon, Oct 17, 2022 at 01:20:49PM -0400, Krzysztof Kozlowski wrote:
> On 17/10/2022 10:53, Johan Hovold wrote:
> > Add bindings for the PCIe QMP PHYs found on SC8280XP.
> > 
> > The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
> > 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
> > PCIe2A and PCIe2B).
> > 
> > The configuration for a specific system can be read from a TCSR register.
> > 
> > Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
> > ---
> >  .../bindings/phy/qcom,qmp-pcie-phy.yaml       | 163 ++++++++++++++++++
> >  1 file changed, 163 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..82da95eaa9d6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> 
> Filename based on compatible, so for example:
> 
> qcom,sc8280xp-qmp-pcie-phy.yaml

Ok, but as I mentioned in my reply to the previous patch, this file is
the one that is expected to be extended with new bindings.

I can't seem to find where this naming scheme is documented now even if
I'm quite sure I've seen it before. Do you have a pointer?

And does this imply that the file name should also include the gen infix
of one of the original compatibles (e.g.
"qcom,sc8280xp-qmp-gen3x4-pcie-phy.yaml")?

> > @@ -0,0 +1,163 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm QMP PHY controller (PCIe)
> > +
> > +maintainers:
> > +  - Vinod Koul <vkoul@...nel.org>
> > +
> > +description:
> > +  QMP PHY controller supports physical layer functionality for a number of
> > +  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> > +      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> > +      - qcom,sc8280xp-qmp-gen3x4-pcie-phy

> > +  qcom,4ln-config-sel:
> > +    description: 4-lane configuration as TCSR syscon phandle, register offset
> > +                 and bit number
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    items:
> > +      maxItems: 3
> 
> You have only one phandle, so you need to describe the items and limit
> their number, like here:
> 
> https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42
> 
> This allows you to skip most of property description.

Ah, thanks, makes perfect sense. I based this one of the in-tree
bindings which had been reviewed by Rob and must have thought it was
some special phandle-array notation to express the same.

Johan