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Message-ID: <20221018121739.0000491e@huawei.com>
Date: Tue, 18 Oct 2022 12:17:39 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Davidlohr Bueso <dave@...olabs.net>
CC: <dan.j.williams@...el.com>, <ira.weiny@...el.com>,
<dave.jiang@...el.com>, <alison.schofield@...el.com>,
<bwidawsk@...nel.org>, <vishal.l.verma@...el.com>,
<a.manzanares@...sung.com>, <linux-cxl@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support
On Mon, 17 Oct 2022 20:00:09 -0700
Davidlohr Bueso <dave@...olabs.net> wrote:
> Introduce a generic irq table for CXL components/features that can have
> standard irq support - DOE requires dynamic vector sizing and is not
> considered here. For now the table is empty.
>
> Create an infrastructure to query the max vectors required for the CXL
> device. Upon successful allocation, users can plug in their respective isr
> at any point thereafter, which is supported by a new cxlds->has_irq flag,
> for example, if the irq setup is not done in the PCI driver, such as
> the case of the CXL-PMU.
>
> Reviewed-by: Dave Jiang <dave.jiang@...el.com>
> Signed-off-by: Davidlohr Bueso <dave@...olabs.net>
> + vectors++;
> + rc = pci_alloc_irq_vectors(pdev, vectors, vectors,
> + PCI_IRQ_MSIX | PCI_IRQ_MSI);
> + if (rc < 0)
> + return rc;
> +
> + if (rc != vectors) {
Just catching up with David Jiang's review of the CPMU driver.
He correctly points out that we won't hit this condition because
we provide minvec to the pci_alloc_irq_vectors() call:
> I don't think you'll hit here since you passed in vectors for min and
> max. You'll get -ENOSPC and return from the earlier check.
>
> https://elixir.bootlin.com/linux/v6.0-rc3/source/drivers/pci/msi/msi.c#L1005
>
> DJ
> + dev_dbg(dev, "Not enough interrupts; use polling instead.\n");
> + /* some got allocated, clean them up */
> + cxl_pci_free_irq_vectors(pdev);
> + return -ENOSPC;
> + }
> +
> + return devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev);
> +}
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