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Message-ID: <CAAhSdy1bjD15c-xnhHv6K9Zsy_fvmNU6w=TyM1hS41MYtJkmTg@mail.gmail.com>
Date: Wed, 19 Oct 2022 17:52:42 +0530
From: Anup Patel <anup@...infault.org>
To: Palmer Dabbelt <palmer@...belt.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Atish Patra <atishp@...shpatra.org>,
Heiko Stuebner <heiko@...ech.de>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Andrew Jones <ajones@...tanamicro.com>,
kernel test robot <lkp@...el.com>,
Anup Patel <apatel@...tanamicro.com>,
Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM
Hi Palmer,
On Wed, Oct 19, 2022 at 5:46 PM Anup Patel <apatel@...tanamicro.com> wrote:
>
> From: Andrew Jones <ajones@...tanamicro.com>
>
> riscv_cbom_block_size and riscv_init_cbom_blocksize() should always
> be available and riscv_init_cbom_blocksize() should always be
> invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This
> is because disabling RISCV_ISA_ZICBOM means "don't use zicbom
> instructions in the kernel" not "pretend there isn't zicbom, even
> when there is". When zicbom is available, whether the kernel enables
> its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests.
> Ensure we can build KVM and that the block size is initialized even
> when compiling without RISCV_ISA_ZICBOM.
>
> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing")
> Reported-by: kernel test robot <lkp@...el.com>
> Signed-off-by: Andrew Jones <ajones@...tanamicro.com>
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Currently, the KVM RISC-V compilation is broken for toolchains not
having Zicbom support.
I plan to take this patch through the KVM RISC-V tree and I will be
sending a PR by the end of this week. Let me know if you want this
patch to go through the RISC-V tree.
Regards,
Anup
> ---
> arch/riscv/mm/cacheflush.c | 41 +++++++++++++++++++++++++++++++++
> arch/riscv/mm/dma-noncoherent.c | 41 ---------------------------------
> 2 files changed, 41 insertions(+), 41 deletions(-)
>
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index 6cb7d96ad9c7..f318b2553612 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -3,6 +3,8 @@
> * Copyright (C) 2017 SiFive
> */
>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> #include <asm/cacheflush.h>
>
> #ifdef CONFIG_SMP
> @@ -86,3 +88,42 @@ void flush_icache_pte(pte_t pte)
> flush_icache_all();
> }
> #endif /* CONFIG_MMU */
> +
> +unsigned int riscv_cbom_block_size;
> +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> +
> +#ifdef CONFIG_RISCV_ISA_ZICBOM
> +void riscv_init_cbom_blocksize(void)
> +{
> + struct device_node *node;
> + unsigned long cbom_hartid;
> + u32 val, probed_block_size;
> + int ret;
> +
> + probed_block_size = 0;
> + for_each_of_cpu_node(node) {
> + unsigned long hartid;
> +
> + ret = riscv_of_processor_hartid(node, &hartid);
> + if (ret)
> + continue;
> +
> + /* set block-size for cbom extension if available */
> + ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> + if (ret)
> + continue;
> +
> + if (!probed_block_size) {
> + probed_block_size = val;
> + cbom_hartid = hartid;
> + } else {
> + if (probed_block_size != val)
> + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> + cbom_hartid, hartid);
> + }
> + }
> +
> + if (probed_block_size)
> + riscv_cbom_block_size = probed_block_size;
> +}
> +#endif
> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> index b0add983530a..d919efab6eba 100644
> --- a/arch/riscv/mm/dma-noncoherent.c
> +++ b/arch/riscv/mm/dma-noncoherent.c
> @@ -8,13 +8,8 @@
> #include <linux/dma-direct.h>
> #include <linux/dma-map-ops.h>
> #include <linux/mm.h>
> -#include <linux/of.h>
> -#include <linux/of_device.h>
> #include <asm/cacheflush.h>
>
> -unsigned int riscv_cbom_block_size;
> -EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> -
> static bool noncoherent_supported;
>
> void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> dev->dma_coherent = coherent;
> }
>
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -void riscv_init_cbom_blocksize(void)
> -{
> - struct device_node *node;
> - unsigned long cbom_hartid;
> - u32 val, probed_block_size;
> - int ret;
> -
> - probed_block_size = 0;
> - for_each_of_cpu_node(node) {
> - unsigned long hartid;
> -
> - ret = riscv_of_processor_hartid(node, &hartid);
> - if (ret)
> - continue;
> -
> - /* set block-size for cbom extension if available */
> - ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> - if (ret)
> - continue;
> -
> - if (!probed_block_size) {
> - probed_block_size = val;
> - cbom_hartid = hartid;
> - } else {
> - if (probed_block_size != val)
> - pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> - cbom_hartid, hartid);
> - }
> - }
> -
> - if (probed_block_size)
> - riscv_cbom_block_size = probed_block_size;
> -}
> -#endif
> -
> void riscv_noncoherent_supported(void)
> {
> WARN(!riscv_cbom_block_size,
> --
> 2.34.1
>
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