linux-kernel - [PATCH 6.0 038/862] mmc: sdhci-tegra: Use actual clock rate for SW tuning correction

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Message-Id: <20221019083251.682421300@linuxfoundation.org>
Date:   Wed, 19 Oct 2022 10:22:05 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Aniruddha TVS Rao <anrao@...dia.com>,
        Prathamesh Shete <pshete@...dia.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Thierry Reding <treding@...dia.com>,
        Ulf Hansson <ulf.hansson@...aro.org>
Subject: [PATCH 6.0 038/862] mmc: sdhci-tegra: Use actual clock rate for SW tuning correction

From: Prathamesh Shete <pshete@...dia.com>

commit b78870e7f41534cc719c295d1f8809aca93aeeab upstream.

Ensure tegra_host member "curr_clk_rate" holds the actual clock rate
instead of requested clock rate for proper use during tuning correction
algorithm. Actual clk rate may not be the same as the requested clk
frequency depending on the parent clock source set. Tuning correction
algorithm depends on certain parameters which are sensitive to current
clk rate. If the host clk is selected instead of the actual clock rate,
tuning correction algorithm may end up applying invalid correction,
which could result in errors

Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process")
Signed-off-by: Aniruddha TVS Rao <anrao@...dia.com>
Signed-off-by: Prathamesh Shete <pshete@...dia.com>
Acked-by: Adrian Hunter <adrian.hunter@...el.com>
Acked-by: Thierry Reding <treding@...dia.com>
Cc: stable@...r.kernel.org
Link: https://lore.kernel.org/r/20221006130622.22900-4-pshete@nvidia.com
Signed-off-by: Ulf Hansson <ulf.hansson@...aro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
 drivers/mmc/host/sdhci-tegra.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -773,7 +773,7 @@ static void tegra_sdhci_set_clock(struct
 		dev_err(dev, "failed to set clk rate to %luHz: %d\n",
 			host_clk, err);
 
-	tegra_host->curr_clk_rate = host_clk;
+	tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk);
 	if (tegra_host->ddr_signaling)
 		host->max_clk = host_clk;
 	else