linux-kernel - [PATCH 2/6] x86: KVM: Enable AMX-FP16 CPUID and expose it to guest

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Date:   Wed, 19 Oct 2022 16:47:30 +0800
From:   Jiaxi Chen <jiaxi.chen@...ux.intel.com>
To:     kvm@...r.kernel.org
Cc:     tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
        dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
        seanjc@...gle.com, pbonzini@...hat.com, ndesaulniers@...gle.com,
        alexandre.belloni@...tlin.com, peterz@...radead.org,
        jiaxi.chen@...ux.intel.com, jpoimboe@...nel.org,
        chang.seok.bae@...el.com, pawan.kumar.gupta@...ux.intel.com,
        babu.moger@....com, jmattson@...gle.com, sandipan.das@....com,
        tony.luck@...el.com, sathyanarayanan.kuppuswamy@...ux.intel.com,
        fenghua.yu@...el.com, keescook@...omium.org,
        jane.malalane@...rix.com, nathan@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH 2/6] x86: KVM: Enable AMX-FP16 CPUID and expose it to guest

From: "Chang S. Bae" <chang.seok.bae@...el.com>

Latest Intel platform Granite Rapids has introduced a new instruction -
AMX-FP16, which performs dot-products of two FP16 tiles and accumulates
the results into a packed single precision tile. This instruction adds
FP16 capability and also allows a FP16 GPU trained model to run faster
without loss of accuracy or added SW overhead.

The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 21]

This patch enables this CPUID in the kernel feature bits and expose it
to guest OS.

Signed-off-by: Chang S. Bae <chang.seok.bae@...el.com>
Signed-off-by: Jiaxi Chen <jiaxi.chen@...ux.intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kvm/cpuid.c               | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 445626cb5779..9313240e3cdd 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -309,6 +309,7 @@
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
 #define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* CMPccXADD instructions */
+#define X86_FEATURE_AMX_FP16		(12*32+21) /* AMX fp16 Support */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 3f745f6fdc43..d983ddb974ba 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -657,7 +657,7 @@ void kvm_set_cpu_caps(void)
 		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
 
 	kvm_cpu_cap_mask(CPUID_7_1_EAX,
-		F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD)
+		F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16)
 	);
 
 	kvm_cpu_cap_mask(CPUID_D_1_EAX,
-- 
2.27.0