| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20221020212610.697729-2-matthew.gerlach@linux.intel.com>
Date: Thu, 20 Oct 2022 14:26:07 -0700
From: matthew.gerlach@...ux.intel.com
To: hao.wu@...el.com, yilun.xu@...el.com, russell.h.weight@...el.com,
basheer.ahmed.muddebihal@...el.com, trix@...hat.com,
mdf@...nel.org, linux-fpga@...r.kernel.org,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
tianfei.zhang@...el.com, corbet@....net,
gregkh@...uxfoundation.org, linux-serial@...r.kernel.org,
jirislaby@...nel.org, geert+renesas@...der.be,
andriy.shevchenko@...ux.intel.com,
niklas.soderlund+renesas@...natech.se, macro@...am.me.uk,
johan@...nel.org, lukas@...ner.de, ilpo.jarvinen@...ux.intel.com,
marpagan@...hat.com
Cc: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: [PATCH v4 1/4] Documentation: fpga: dfl: Add documentation for DFHv1
From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Add documentation describing the extensions provided by Version
1 of the Device Feature Header (DFHv1).
Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
---
v4: Remove marketing speak and separate v0 and v1 descriptions.
Fix errors reported by "make htmldocs".
v3: no change
v2: s/GUILD/GUID/
add picture
---
Documentation/fpga/dfl.rst | 96 ++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index 15b670926084..12365be435a8 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -561,6 +561,102 @@ new DFL feature via UIO direct access, its feature id should be added to the
driver's id_table.
+Device Feature Header - Version 0
+===========================================
+The format of Version 0 of a Device Feature Header (DFH) is shown below::
+
+ +-----------------------------------------------------------------------+
+ |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00
+ +-----------------------------------------------------------------------+
+ |63 GUID_L 0| 0x08
+ +-----------------------------------------------------------------------+
+ |63 GUID_H 0| 0x10
+ +-----------------------------------------------------------------------+
+
+Offset 0x00
+Type - The type of DFH (e.g. FME, AFU, or private feature).
+DFH VER - The version of the DFH.
+Rsvd - Currently unused.
+EOL - Set if this DFH is the end of the Device Feature List (DFL).
+Next - The offset of the next DFH in the DFL from the start of the DFH.
+If EOL is set, Next refers to size of mmio for last feature in the list.
+ID - If Type field is 'private feature', then ID of the private feature.
+
+Offset 0x08
+GUID_L - Least significant 64 bits of a 128 bit Globally Unique Identifier
+if Type is FME or AFU.
+
+Offset 0x10
+GUID_H - Most significant 64 bits of a 128 bit Globally Unique Identifier
+if Type is FME or AFU.
+
+
+Device Feature Header - Version 1
+===========================================
+The format of Version 1 of a Device Feature Header (DFH) is shown below::
+
+ +-----------------------------------------------------------------------+
+ |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00
+ +-----------------------------------------------------------------------+
+ |63 GUID_L 0| 0x08
+ +-----------------------------------------------------------------------+
+ |63 GUID_H 0| 0x10
+ +-----------------------------------------------------------------------+
+ |63 Address/Offset 1| Rel 0| 0x18
+ +-----------------------------------------------------------------------+
+ |63 Reg Size 32|Params 31|30 Group 16|15 Instance 0| 0x20
+ +-----------------------------------------------------------------------+
+ |63 Next 34|RSV33|EOP32|31 Param Version 16|15 Param ID 0| 0x28
+ +-----------------------------------------------------------------------+
+ |63 Parameter Data 0| 0x30
+ +-----------------------------------------------------------------------+
+
+ ...
+
+ +-----------------------------------------------------------------------+
+ |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0|
+ +-----------------------------------------------------------------------+
+ |63 Parameter Data 0|
+ +-----------------------------------------------------------------------+
+
+Offset 0x00
+Type - The type of DFH (e.g. FME, AFU, or private feature).
+DFH VER - The version of the DFH.
+Rsvd - Currently unused.
+EOL - Set if this DFH is the end of the Device Feature List (DFL).
+Next - The offset of the next DFH in the DFL from the start of the DFH.
+If EOL is set, Next refers to size of mmio for last feature in the list.
+ID - If Type field is 'private feature', then ID of the private feature.
+
+Offset 0x08
+GUID_L - Least significant 64 bits of a 128 bit Globally Unique Identifier.
+
+Offset 0x10
+GUID_H - Most significant 64 bits of a 128 bit Globally Unique Identifier
+if Type is FME or AFU.
+
+Offset 0x18
+Address/Offset - If Rel bit is set, then high 63 bits of a 16 bit aligned
+absolute address for the location of the feature's registers.
+If Rel bit is clear, then the feature's registers start at the
+offset from the start of the DFH.
+
+Offset 0x20
+Reg Size - Size of feature's register set.
+Params - Set if DFH has one or more parameter blocks.
+Group - Id of group if feature is part of a group.
+Instance - Id of instance of feature within a group.
+
+Offset 0x28 if feature has parameters
+Next - High 30 bits of a 32 bit aligned offset to the next parameter block.
+If EOP set, size of last parameter.
+Param Version - Version of Param ID.
+Param ID - ID of parameter.
+
+Offset 0x30
+Parameter Data - Parameter data whose size and format is defined by version
+and ID of the parameter.
+
Open discussion
===============
FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
--
2.25.1
Powered by blists - more mailing lists