linux-kernel - Re: [PATCH v2 07/12] cxl: Remove dev_is_cxl_root_child() check in devm_cxl_enumerate

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Message-ID: <552e105ca749fae4517ef053b0439cb3eecd1e4c.camel@intel.com>
Date:   Fri, 21 Oct 2022 06:32:33 +0000
From:   "Verma, Vishal L" <vishal.l.verma@...el.com>
To:     "Williams, Dan J" <dan.j.williams@...el.com>,
        "Schofield, Alison" <alison.schofield@...el.com>,
        "bwidawsk@...nel.org" <bwidawsk@...nel.org>,
        "rrichter@....com" <rrichter@....com>,
        "Weiny, Ira" <ira.weiny@...el.com>
CC:     "Jonathan.Cameron@...wei.com" <Jonathan.Cameron@...wei.com>,
        "dave@...olabs.net" <dave@...olabs.net>,
        "linux-cxl@...r.kernel.org" <linux-cxl@...r.kernel.org>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "lenb@...nel.org" <lenb@...nel.org>,
        "rafael@...nel.org" <rafael@...nel.org>
Subject: Re: [PATCH v2 07/12] cxl: Remove dev_is_cxl_root_child() check in
 devm_cxl_enumerate_ports()

On Thu, 2022-10-20 at 22:38 -0700, Dan Williams wrote:
> Robert Richter wrote:
> > 

<..>

> 
> With that scheme in place and some cxl-cli fixups from Vishal we are
> seeing:
> 
> # cxl list -BEMPTu
> {
>   "bus":"root0",
>   "provider":"ACPI.CXL",
>   "nr_dports":1,
>   "dports":[
>     {
>       "dport":"pci0000:38",
>       "id":"0x31"
>     }
>   ],
>   "endpoints:root0":[
>     {
>       "endpoint":"endpoint1",
>       "host":"mem0",
>       "depth":1,
>       "memdev":{
>         "memdev":"mem0",
>         "pmem_size":0,
>         "ram_size":"16.00 GiB (17.18 GB)",
>         "serial":"0",
>         "numa_node":0,
>         "host":"0000:38:00.0"
>       }
>     }
>   ]
> }

I was waiting to post the cxl-cli patches for this until the kernel
discussion settles - but maybe this topology layout is settled enough?

In the meanwhile I've pushed a branch with these fixups here:
https://github.com/pmem/ndctl/tree/vv/rch-support

> 
> Does that make sense? I think this patchset gets a lot simpler if it
> does not try to make devm_cxl_enumerate_ports() understand the RCH
> topology.