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Message-ID: <d265dae0-fe4b-8ac0-fb9e-2a7345b279a2@linux.intel.com>
Date: Fri, 21 Oct 2022 11:28:58 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
cc: hao.wu@...el.com, yilun.xu@...el.com, russell.h.weight@...el.com,
basheer.ahmed.muddebihal@...el.com, trix@...hat.com,
mdf@...nel.org, linux-fpga@...r.kernel.org,
linux-doc@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>,
tianfei.zhang@...el.com, corbet@....net,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-serial <linux-serial@...r.kernel.org>,
Jiri Slaby <jirislaby@...nel.org>, geert+renesas@...der.be,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
niklas.soderlund+renesas@...natech.se, macro@...am.me.uk,
johan@...nel.org, Lukas Wunner <lukas@...ner.de>,
marpagan@...hat.com
Subject: Re: [PATCH v4 1/4] Documentation: fpga: dfl: Add documentation for
DFHv1
On Thu, 20 Oct 2022, matthew.gerlach@...ux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>
> Add documentation describing the extensions provided by Version
> 1 of the Device Feature Header (DFHv1).
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> ---
> v4: Remove marketing speak and separate v0 and v1 descriptions.
> Fix errors reported by "make htmldocs".
>
> v3: no change
>
> v2: s/GUILD/GUID/
> add picture
> ---
> Documentation/fpga/dfl.rst | 96 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> index 15b670926084..12365be435a8 100644
> --- a/Documentation/fpga/dfl.rst
> +++ b/Documentation/fpga/dfl.rst
> @@ -561,6 +561,102 @@ new DFL feature via UIO direct access, its feature id should be added to the
> driver's id_table.
>
>
> +Device Feature Header - Version 0
> +===========================================
> +The format of Version 0 of a Device Feature Header (DFH) is shown below::
> +
> + +-----------------------------------------------------------------------+
> + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00
> + +-----------------------------------------------------------------------+
> + |63 GUID_L 0| 0x08
> + +-----------------------------------------------------------------------+
> + |63 GUID_H 0| 0x10
> + +-----------------------------------------------------------------------+
> +
> +Offset 0x00
> +Type - The type of DFH (e.g. FME, AFU, or private feature).
> +DFH VER - The version of the DFH.
> +Rsvd - Currently unused.
> +EOL - Set if this DFH is the end of the Device Feature List (DFL).
> +Next - The offset of the next DFH in the DFL from the start of the DFH.
> +If EOL is set, Next refers to size of mmio for last feature in the list.
> +ID - If Type field is 'private feature', then ID of the private feature.
> +
> +Offset 0x08
> +GUID_L - Least significant 64 bits of a 128 bit Globally Unique Identifier
> +if Type is FME or AFU.
> +
> +Offset 0x10
> +GUID_H - Most significant 64 bits of a 128 bit Globally Unique Identifier
> +if Type is FME or AFU.
> +
> +
> +Device Feature Header - Version 1
> +===========================================
While this is structurally better than the previous one. I'd still include
at least one paragraph about the purpose. Something along these lines
(picked from v3 + edited the marketing speak/v0 compare away from it):
Version 1 of the Device Feature Header (DFHv1) provides flexibility and
extensibility to hardware designs using Device Feature Lists. It is a
standardized mechanism for features to describe parameters/capabilities to
software.
With DFHv1:
* GUID is mandatory for all types
* The register space of the feature is decoupled from the location of the DFH
* A list of parameter values associates to a particular feature.
After that, the header itself makes much more sense already.
> +The format of Version 1 of a Device Feature Header (DFH) is shown below::
> +
> + +-----------------------------------------------------------------------+
> + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00
> + +-----------------------------------------------------------------------+
> + |63 GUID_L 0| 0x08
> + +-----------------------------------------------------------------------+
> + |63 GUID_H 0| 0x10
> + +-----------------------------------------------------------------------+
> + |63 Address/Offset 1| Rel 0| 0x18
Should this mention it's addr/offs of registers? As is it's bit hard to
figure out from the diagram w/o the extra description. I think you have
plenty of space for adding that extra bit of info.
> + +-----------------------------------------------------------------------+
> + |63 Reg Size 32|Params 31|30 Group 16|15 Instance 0| 0x20
> + +-----------------------------------------------------------------------+
> + |63 Next 34|RSV33|EOP32|31 Param Version 16|15 Param ID 0| 0x28
> + +-----------------------------------------------------------------------+
> + |63 Parameter Data 0| 0x30
> + +-----------------------------------------------------------------------+
> +
> + ...
> +
> + +-----------------------------------------------------------------------+
> + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0|
> + +-----------------------------------------------------------------------+
> + |63 Parameter Data 0|
> + +-----------------------------------------------------------------------+
> +
> +Offset 0x00
> +Type - The type of DFH (e.g. FME, AFU, or private feature).
> +DFH VER - The version of the DFH.
> +Rsvd - Currently unused.
> +EOL - Set if this DFH is the end of the Device Feature List (DFL).
> +Next - The offset of the next DFH in the DFL from the start of the DFH.
> +If EOL is set, Next refers to size of mmio for last feature in the list.
> +ID - If Type field is 'private feature', then ID of the private feature.
> +
> +Offset 0x08
> +GUID_L - Least significant 64 bits of a 128 bit Globally Unique Identifier.
> +
> +Offset 0x10
> +GUID_H - Most significant 64 bits of a 128 bit Globally Unique Identifier
> +if Type is FME or AFU.
A copy-paste error?
> +
> +Offset 0x18
> +Address/Offset - If Rel bit is set, then high 63 bits of a 16 bit aligned
> +absolute address for the location of the feature's registers.
> +If Rel bit is clear, then the feature's registers start at the
> +offset from the start of the DFH.
> +
> +Offset 0x20
> +Reg Size - Size of feature's register set.
> +Params - Set if DFH has one or more parameter blocks.
> +Group - Id of group if feature is part of a group.
> +Instance - Id of instance of feature within a group.
> +
> +Offset 0x28 if feature has parameters
> +Next - High 30 bits of a 32 bit aligned offset to the next parameter block.
> +If EOP set, size of last parameter.
> +Param Version - Version of Param ID.
> +Param ID - ID of parameter.
> +
> +Offset 0x30
> +Parameter Data - Parameter data whose size and format is defined by version
> +and ID of the parameter.
I'd reverse the order and say "ID and version" (kind of major thing
first).
> +
> Open discussion
> ===============
> FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
>
--
i.
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