Message-ID: <f8a64289-6560-7d75-461c-39b7a612e9c2@loongson.cn>
Date:   Fri, 21 Oct 2022 09:58:57 +0800
From:   Jianmin Lv <lvjianmin@...ngson.cn>
To:     Bjorn Helgaas <helgaas@...nel.org>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>, linux-kernel@...r.kernel.org,
        loongarch@...ts.linux.dev, Jiaxun Yang <jiaxun.yang@...goat.com>,
        Huacai Chen <chenhuacai@...ngson.cn>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Len Brown <lenb@...nel.org>, rafael@...nel.org,
        linux-pci@...r.kernel.org, linux-acpi@...r.kernel.org
Subject: Re: [PATCH V4 1/4] ACPI / PCI: fix LPIC IRQ model default PCI IRQ
 polarity



On 2022/10/21 上午12:47, Bjorn Helgaas wrote:
> On Thu, Oct 20, 2022 at 04:22:02PM +0800, Jianmin Lv wrote:
>> On LoongArch ACPI based systems, the PCI devices (e.g. sata
>> controlers and PCI-to-to PCI bridge controlers) existed in
>> Loongson chipsets output high-level interrupt signal to the
>> interrupt controller they connected to,
> 
> I assume the active high behavior is hardware behavior that is
> independent of the fact that you're using ACPI firmware on the
> hardware.  If so, I would omit "ACPI based".
> 
> s/sata/SATA/
> s/controlers/controllers/ (twice)
> s/PCI-to-to PCI/PCI-to-PCI/
> s/existed in/in/
> s/they connected/they are connected/
> 

Ok, thanks, I'll improve them again.

>> while the IRQs are
>> active low from the perspective of PCI(in 2.2.6. Interrupt
>> Pins, "Interrupts on PCI are optional and defined as level
>> sensitive, asserted low),
> 
> I don't think you need this spec reference, since "asserted low" is
> the standard thing that happens everywhere.  But if you do want it, it
> needs to specify which spec it refers to, e.g., "Conventional PCI
> r3.0, sec 2.2.6" so it's not confused with the PCIe spec.
> 
> The quote from the spec itself should be terminated with a close quote
> ("), i.e.,
> 
>    "Interrupts on PCI ... asserted low"
> 

Ok, thanks, I'll specify spec version with correct pattern.

>> which means that the interrupt
>> output of PCI devices plugged into PCI-to-to PCI bridges of
>> Loongson chipset will be also converted to high-level. So
>> high level triggered type is required to be passed to
>> acpi_register_gsi() when creating mappings for PCI devices.
> 
> This is the part where I was hoping for a reference to a spec that
> talks about how PCI interrupts are inverted.  The inverter is the part
> that's special here.
> 
> I see that ACPI r6.5, sec 5.2.12, mentions LPIC, but it doesn't
> mention the inverter.  It has a lot more mentions of GIC, but also no
> details about an inverter.  I suppose that would be in the GIC spec,
> which I'm not familiar with.
> 
> The point is that one should be able to write this code from a spec,
> without having to empirically discover the interrupt polarity.  What
> spec tells you about using ACTIVE_HIGH here?
> 
Yes, no mentions for the inverter in ACPI spec, the description about
device interrupt type can be found in Loongson chipset manual:

https://github.com/loongson/LoongArch-Documentation/blob/main/docs/Loongson-7A1000-usermanual-EN/interrupt-controller/device-interrupt-types.adoc

where the interrupts coming from interrupt source are level triggered 
and active high except some specific device such as AC97 DMA and GPIO.

> s/PCI-to-to PCI/PCI-to-PCI/ again
>
> Rewrap the log to fill 75 columns like the rest of the history.
> 
Ok, thanks.

>> Signed-off-by: Jianmin Lv <lvjianmin@...ngson.cn>
>> ---
>>   drivers/acpi/pci_irq.c | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
>> index 08e15774fb9f..ff30ceca2203 100644
>> --- a/drivers/acpi/pci_irq.c
>> +++ b/drivers/acpi/pci_irq.c
>> @@ -387,13 +387,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
>>   	u8 pin;
>>   	int triggering = ACPI_LEVEL_SENSITIVE;
>>   	/*
>> -	 * On ARM systems with the GIC interrupt model, level interrupts
>> +	 * On ARM systems with the GIC interrupt model, or LoongArch
>> +	 * systems with the LPIC interrupt model, level interrupts
> 
> Is "LoongArch" required in this comment?  Might the LPIC model be used
> on non-LoongArch systems?
> 
Just like GIC is restricted to ARM, and LPIC is restricted to LoongArch, 
as you mentioned below. So LPIC model will be not used on non-LoongArch 
systems.

> I see it follows the example of "ARM systems".  In my opinion, "ARM"
> probably should be removed, too, because the code checks only for GIC
> or LPIC; it doesn't check for ARM or LoongArch.
> 
> If GIC is restricted to ARM and LPIC is restricted to LoongArch,
> that's fine, but that constraint should be expressed somewhere else
> and doesn't need to be repeated here.
> 
Though the definition and constraints for GIC and LPIC are explicitly 
expressed in ACPI spec, to be clear, repeating the relation here only 
with short words maybe worthy so that people understand the workaround 
conveniently without having to referencing ACPI spec, right?

>>   	 * are always polarity high by specification; PCI legacy
>>   	 * IRQs lines are inverted before reaching the interrupt
>>   	 * controller and must therefore be considered active high
>>   	 * as default.
>>   	 */
>> -	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ?
>> +	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ||
>> +		       acpi_irq_model == ACPI_IRQ_MODEL_LPIC ?
>>   				      ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW;
>>   	char *link = NULL;
>>   	char link_desc[16];
>> -- 
>> 2.31.1
>>

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