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Message-ID: <20221022114424.515572025@infradead.org>
Date: Sat, 22 Oct 2022 13:14:04 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: x86@...nel.org, willy@...radead.org, torvalds@...ux-foundation.org,
akpm@...ux-foundation.org
Cc: linux-kernel@...r.kernel.org, peterz@...radead.org,
linux-mm@...ck.org, aarcange@...hat.com,
kirill.shutemov@...ux.intel.com, jroedel@...e.de, ubizjak@...il.com
Subject: [PATCH 01/13] mm: Update ptep_get_lockless()s comment
Improve the comment.
Suggested-by: Matthew Wilcox <willy@...radead.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
---
include/linux/pgtable.h | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
--- a/include/linux/pgtable.h
+++ b/include/linux/pgtable.h
@@ -260,15 +260,12 @@ static inline pte_t ptep_get(pte_t *ptep
#ifdef CONFIG_GUP_GET_PTE_LOW_HIGH
/*
- * WARNING: only to be used in the get_user_pages_fast() implementation.
- *
- * With get_user_pages_fast(), we walk down the pagetables without taking any
- * locks. For this we would like to load the pointers atomically, but sometimes
- * that is not possible (e.g. without expensive cmpxchg8b on x86_32 PAE). What
- * we do have is the guarantee that a PTE will only either go from not present
- * to present, or present to not present or both -- it will not switch to a
- * completely different present page without a TLB flush in between; something
- * that we are blocking by holding interrupts off.
+ * For walking the pagetables without holding any locks. Some architectures
+ * (eg x86-32 PAE) cannot load the entries atomically without using expensive
+ * instructions. We are guaranteed that a PTE will only either go from not
+ * present to present, or present to not present -- it will not switch to a
+ * completely different present page without a TLB flush inbetween; which we
+ * are blocking by holding interrupts off.
*
* Setting ptes from not present to present goes:
*
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