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Message-ID: <0e0eff12-d8ea-72e9-d135-4259dda9a750@gmail.com>
Date: Sat, 22 Oct 2022 20:50:46 +0900
From: Chanwoo Choi <cwchoi00@...il.com>
To: Arnd Bergmann <arnd@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Tomasz Figa <tomasz.figa@...il.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: linux-kernel@...r.kernel.org, Ben Dooks <ben-linux@...ff.org>,
Simtec Linux Team <linux@...tec.co.uk>,
Arnd Bergmann <arnd@...db.de>,
Alim Akhtar <alim.akhtar@...sung.com>,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH 11/21] clk: remove s3c24xx driver
Hi Arnd,
On 22. 10. 22. 05:27, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@...db.de>
>
> The s3c24xx platform is gone, so the clk driver can be removed as
> well.
>
> Signed-off-by: Arnd Bergmann <arnd@...db.de>
> ---
> MAINTAINERS | 1 -
> drivers/clk/samsung/Kconfig | 32 --
> drivers/clk/samsung/Makefile | 4 -
> drivers/clk/samsung/clk-s3c2410-dclk.c | 440 ---------------------
> drivers/clk/samsung/clk-s3c2410.c | 446 ----------------------
> drivers/clk/samsung/clk-s3c2412.c | 254 ------------
> drivers/clk/samsung/clk-s3c2443.c | 438 ---------------------
> include/linux/platform_data/clk-s3c2410.h | 19 -
> 8 files changed, 1634 deletions(-)
> delete mode 100644 drivers/clk/samsung/clk-s3c2410-dclk.c
> delete mode 100644 drivers/clk/samsung/clk-s3c2410.c
> delete mode 100644 drivers/clk/samsung/clk-s3c2412.c
> delete mode 100644 drivers/clk/samsung/clk-s3c2443.c
> delete mode 100644 include/linux/platform_data/clk-s3c2410.h
(snip)
I think that it should remove the pll code related to s3c24xx as following:
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index fe383471c5f0..0daea2aadce4 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1061,48 +1061,6 @@ static void samsung_s3c2410_upll_disable(struct clk_hw *hw)
samsung_s3c2410_pll_enable(hw, 7, false);
}
-static const struct clk_ops samsung_s3c2410_mpll_clk_min_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
-};
-
-static const struct clk_ops samsung_s3c2410_upll_clk_min_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_upll_enable,
- .disable = samsung_s3c2410_upll_disable,
-};
-
-static const struct clk_ops samsung_s3c2440_mpll_clk_min_ops = {
- .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
-};
-
-static const struct clk_ops samsung_s3c2410_mpll_clk_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
- .round_rate = samsung_pll_round_rate,
- .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
-static const struct clk_ops samsung_s3c2410_upll_clk_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_upll_enable,
- .disable = samsung_s3c2410_upll_disable,
- .round_rate = samsung_pll_round_rate,
- .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
-static const struct clk_ops samsung_s3c2440_mpll_clk_ops = {
- .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
- .round_rate = samsung_pll_round_rate,
- .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
/*
* PLL2550x Clock Type
*/
@@ -1530,24 +1488,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
else
init.ops = &samsung_pll46xx_clk_ops;
break;
- case pll_s3c2410_mpll:
- if (!pll->rate_table)
- init.ops = &samsung_s3c2410_mpll_clk_min_ops;
- else
- init.ops = &samsung_s3c2410_mpll_clk_ops;
- break;
- case pll_s3c2410_upll:
- if (!pll->rate_table)
- init.ops = &samsung_s3c2410_upll_clk_min_ops;
- else
- init.ops = &samsung_s3c2410_upll_clk_ops;
- break;
- case pll_s3c2440_mpll:
- if (!pll->rate_table)
- init.ops = &samsung_s3c2440_mpll_clk_min_ops;
- else
- init.ops = &samsung_s3c2440_mpll_clk_ops;
- break;
case pll_2550x:
init.ops = &samsung_pll2550x_clk_ops;
break;
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a9892c2d1f57..5d5a58d40e7e 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,9 +25,6 @@ enum samsung_pll_type {
pll_6552,
pll_6552_s3c2416,
pll_6553,
- pll_s3c2410_mpll,
- pll_s3c2410_upll,
- pll_s3c2440_mpll,
pll_2550x,
pll_2550xx,
pll_2650x,
@@ -56,24 +53,6 @@ enum samsung_pll_type {
.sdiv = (_s), \
}
-#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
- { \
- .rate = PLL_VALID_RATE(_fin, _rate, \
- _m + 8, _p + 2, _s, 0, 16), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
- { \
- .rate = PLL_VALID_RATE(_fin, _rate, \
- 2 * (_m + 8), _p + 2, _s, 0, 16), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
{ \
.rate = PLL_VALID_RATE(_fin, _rate, \
--
Best Regards,
Samsung Electronics
Chanwoo Choi
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