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Message-ID: <CAFBinCDWP78Eft63G_QpDH28LibUZF__GNwnBVLcM85dQO8XnA@mail.gmail.com>
Date: Sat, 22 Oct 2022 12:13:43 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Amjad Ouled-Ameur <aouledameur@...libre.com>
Cc: Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Mark Brown <broonie@...nel.org>,
linux-amlogic@...ts.infradead.org, Da Xue <da@...re.computer>,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 2/4] spi: meson-spicc: Use pinctrl to drive CLK line
when idle
On Fri, Oct 21, 2022 at 3:31 PM Amjad Ouled-Ameur
<aouledameur@...libre.com> wrote:
>
> Between SPI transactions, all SPI pins are in HiZ state. When using the SS
> signal from the SPICC controller it's not an issue because when the
> transaction resumes all pins come back to the right state at the same time
> as SS.
>
> The problem is when we use CS as a GPIO. In fact, between the GPIO CS
> state change and SPI pins state change from idle, you can have a missing or
> spurious clock transition.
>
> Set a bias on the clock depending on the clock polarity requested before CS
> goes active, by passing a special "idle-low" and "idle-high" pinctrl state
> and setting the right state at a start of a message
>
> Reported-by: Da Xue <da@...re.computer>
> Signed-off-by: Neil Armstrong <narmstrong@...libre.com>
> Signed-off-by: Amjad Ouled-Ameur <aouledameur@...libre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
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