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Message-ID: <0ac3dc40-080a-f843-f616-7a9fdd78afaf@kernel.org>
Date:   Mon, 24 Oct 2022 08:37:06 +0200
From:   Jiri Slaby <jirislaby@...nel.org>
To:     Sherry Sun <sherry.sun@....com>, gregkh@...uxfoundation.org,
        lukas@...ner.de, ilpo.jarvinen@...ux.intel.com
Cc:     linux-serial@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-imx@....com
Subject: Re: [PATCH V3] tty: serial: fsl_lpuart: don't break the on-going
 transfer when global reset

On 20. 10. 22, 15:19, Sherry Sun wrote:
> @@ -2636,6 +2610,54 @@ static const struct serial_rs485 lpuart_rs485_supported = {
>   	/* delay_rts_* and RX_DURING_TX are not supported */
>   };
>   
> +static int lpuart_global_reset(struct lpuart_port *sport)
> +{
> +	struct uart_port *port = &sport->port;
> +	void __iomem *global_addr;
> +	unsigned long ctrl, bd;
> +	unsigned int val = 0;
> +	int ret;
> +
> +	ret = clk_prepare_enable(sport->ipg_clk);
> +	if (ret) {
> +		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> +		/*
> +		 * If the transmitter is used by earlycon, wait for transmit engine to
> +		 * complete and then reset.
> +		 */
> +		ctrl = lpuart32_read(port, UARTCTRL);
> +		if (ctrl & UARTCTRL_TE) {
> +			bd = lpuart32_read(&sport->port, UARTBAUD);
> +			if (read_poll_timeout_atomic(lpuart32_tx_empty, val, val, 1, 100000,
> +						     false, port)) {

Ah, this is not atomic context (clk_prepare_enable() above and 
usleep_range() below), so no need for _atomic here too.

thanks,
-- 
js
suse labs

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