linux-kernel - Re: [PATCH v4 2/4] fpga: dfl: Add DFHv1 Register Definitions

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Date:   Mon, 24 Oct 2022 08:03:45 -0700 (PDT)
From:   matthew.gerlach@...ux.intel.com
To:     Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
cc:     hao.wu@...el.com, yilun.xu@...el.com, russell.h.weight@...el.com,
        basheer.ahmed.muddebihal@...el.com, trix@...hat.com,
        mdf@...nel.org, linux-fpga@...r.kernel.org,
        linux-doc@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>,
        tianfei.zhang@...el.com, corbet@....net,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        linux-serial <linux-serial@...r.kernel.org>,
        Jiri Slaby <jirislaby@...nel.org>, geert+renesas@...der.be,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        niklas.soderlund+renesas@...natech.se, macro@...am.me.uk,
        johan@...nel.org, Lukas Wunner <lukas@...ner.de>,
        marpagan@...hat.com,
        Basheer Ahmed Muddebihal 
        <basheer.ahmed.muddebihal@...ux.intel.com>
Subject: Re: [PATCH v4 2/4] fpga: dfl: Add DFHv1 Register Definitions



On Fri, 21 Oct 2022, Ilpo Järvinen wrote:

> On Thu, 20 Oct 2022, matthew.gerlach@...ux.intel.com wrote:
>
>> From: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@...ux.intel.com>
>>
>> This patch adds the definitions for DFHv1 header and related register
>> bitfields.
>>
>> Signed-off-by: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@...ux.intel.com>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>> ---
>> v4: s/MSIX/MSI_X/g
>>     move kerneldoc to implementation
>>     don't change copyright date
>>
>> v3:
>>     keep DFHv1 definitions "hidden" in drivers/fpga/dfl.h
>>
>> v2: clean up whitespace and one line comments
>>     remove extra space in commit
>>     use uniform number of digits in constants
>>     don't change copyright date because of removed content
>>
>> dfl.h s/MSIX/MSI_X/g move kerneldoc
>> ---
>>  drivers/fpga/dfl.h  | 33 +++++++++++++++++++++++++++++++++
>>  include/linux/dfl.h | 11 +++++++++++
>>  2 files changed, 44 insertions(+)
>>
>> diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
>> index 06cfcd5e84bb..45e6e1359a67 100644
>> --- a/drivers/fpga/dfl.h
>> +++ b/drivers/fpga/dfl.h
>> @@ -74,11 +74,44 @@
>>  #define DFH_REVISION		GENMASK_ULL(15, 12)	/* Feature revision */
>>  #define DFH_NEXT_HDR_OFST	GENMASK_ULL(39, 16)	/* Offset to next DFH */
>>  #define DFH_EOL			BIT_ULL(40)		/* End of list */
>> +#define DFH_VERSION		GENMASK_ULL(59, 52)	/* DFH version */
>>  #define DFH_TYPE		GENMASK_ULL(63, 60)	/* Feature type */
>>  #define DFH_TYPE_AFU		1
>>  #define DFH_TYPE_PRIVATE	3
>>  #define DFH_TYPE_FIU		4
>>
>> +/*
>> + * DFHv1 Register Offset definitons
>> + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA
>> + * as common header registers
>> + */
>> +#define DFHv1_CSR_ADDR		0x18  /* CSR Register start address */
>> +#define DFHv1_CSR_SIZE_GRP	0x20  /* Size of Reg Block and Group/tag */
>> +#define DFHv1_PARAM_HDR		0x28  /* Optional First Param header */
>> +
>> +/*
>> + * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start),
>> + * 1'b1 = absolute (ARM or other non-PCIe use)
>> + */
>> +#define DFHv1_CSR_ADDR_REL	BIT_ULL(0)
>> +
>> +/* CSR Header Register Bit Definitions */
>> +#define DFHv1_CSR_ADDR_MASK       GENMASK_ULL(63, 1)  /* 63:1 of CSR address */
>> +
>> +/* CSR SIZE Goup Register Bit Definitions */
>> +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID	GENMASK_ULL(15, 0)	/* Enumeration instantiated IP */
>> +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID	GENMASK_ULL(30, 16)	/* Group Features/interfaces */
>> +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS	BIT_ULL(31)		/* Presence of Parameters */
>> +#define DFHv1_CSR_SIZE_GRP_SIZE		GENMASK_ULL(63, 32)	/* Size of CSR Block in bytes */
>
> SIZE -> SZ would remove two letters w/o loss of info (remember to
> rename the offset too if you make this change).
>
>> +/* PARAM Header Register Bit Definitions */
>> +#define DFHv1_PARAM_HDR_ID		GENMASK_ULL(15, 0) /* Id of this Param  */
>> +#define DFHv1_PARAM_HDR_VERSION		GENMASK_ULL(31, 16) /* Version Param */
>> +#define DFHv1_PARAM_HDR_NEXT_OFFSET	GENMASK_ULL(63, 32) /* Offset of next Param */
>> +#define DFHv1_PARAM_HDR_NEXT_EOL	BIT_ULL(0)
>> +#define DFHv1_PARAM_HDR_NEXT_MASK	GENMASK_ULL(1, 0)
>> +#define DFHv1_PARAM_DATA		0x08  /* Offset of Param data from Param header */
>> +
>>  /* Next AFU Register Bitfield */
>>  #define NEXT_AFU_NEXT_DFH_OFST	GENMASK_ULL(23, 0)	/* Offset to next AFU */
>>
>> diff --git a/include/linux/dfl.h b/include/linux/dfl.h
>> index 431636a0dc78..fea9e16d35b6 100644
>> --- a/include/linux/dfl.h
>> +++ b/include/linux/dfl.h
>> @@ -11,6 +11,17 @@
>>  #include <linux/device.h>
>>  #include <linux/mod_devicetable.h>
>>
>> +#define DFHv1_PARAM_ID_MSI_X		0x1
>> +#define DFHv1_PARAM_MSI_X_STARTV	0x0
>> +#define DFHv1_PARAM_MSI_X_NUMV		0x4
>> +
>> +#define DFHv1_PARAM_ID_CLK_FRQ    0x2
>> +#define DFHv1_PARAM_ID_FIFO_LEN   0x3
>> +
>> +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4
>> +#define DFHv1_PARAM_ID_REG_WIDTH  GENMASK_ULL(63, 32)
>> +#define DFHv1_PARAM_ID_REG_SHIFT  GENMASK_ULL(31, 0)
>
> Any particular reason why MSI_X parameters are given as offsets and
> these REG_LAYOUT ones as bitfields (both are 32-bit)?

I agree that it would be much better to be consistent.

>
> The naming here would indicate that DFHv1_PARAM_ID_REG_WIDTH is one of the
> parameters but it's part of param data instead. I suppose you'd want
> DFHv1_PARAM_REG_LAYOUT_WIDTH instead.

Thanks for the naming suggestions.

>
> -- 
> i.
>
>