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Message-ID: <Y1btZRX/e+c+UDyv@spud>
Date: Mon, 24 Oct 2022 20:54:13 +0100
From: Conor Dooley <conor@...nel.org>
To: Anup Patel <apatel@...tanamicro.com>, arnd@...db.de
Cc: Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Atish Patra <atishp@...shpatra.org>,
Heiko Stuebner <heiko@...ech.de>,
Arnd Bergmann <arnd@...db.de>,
Anup Patel <anup@...infault.org>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Mayuresh Chitale <mchitale@...tanamicro.com>
Subject: Re: [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt
On Thu, Oct 20, 2022 at 01:28:44PM +0530, Anup Patel wrote:
> Currently, the memremap() called with MEMREMAP_WB maps memory using
> the generic ioremap() function which breaks on system with Svpbmt
> because memory mapped using _PAGE_IOREMAP page attributes is treated
> as strongly-ordered non-cacheable IO memory.
>
> To address this, we implement RISC-V specific arch_memremap_wb()
> which maps memory using _PAGE_KERNEL page attributes resulting in
> write-back cacheable mapping on systems with Svpbmt.
>
> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> Co-developed-by: Mayuresh Chitale <mchitale@...tanamicro.com>
> Signed-off-by: Mayuresh Chitale <mchitale@...tanamicro.com>
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
Hey Arnd,
Does this look okay to you now?
Thanks,
Conor.
> ---
> arch/riscv/include/asm/io.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index 92080a227937..42497d487a17 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
>
> #include <asm-generic/io.h>
>
> +#ifdef CONFIG_MMU
> +#define arch_memremap_wb(addr, size) \
> + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL))
> +#endif
> +
> #endif /* _ASM_RISCV_IO_H */
> --
> 2.34.1
>
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