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Message-ID: <CAGXv+5EwrRqNuqunzLHtRyZ+AMyO1DDwP01TC9CjbxHnRxbH0g@mail.gmail.com>
Date: Mon, 24 Oct 2022 15:06:35 -0700
From: Chen-Yu Tsai <wenst@...omium.org>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Cc: sboyd@...nel.org, mturquette@...libre.com, matthias.bgg@...il.com,
miles.chen@...iatek.com, nfraprado@...labora.com,
rex-bc.chen@...iatek.com, chun-jie.chen@...iatek.com,
jose.exposito89@...il.com, yangyingliang@...wei.com,
msp@...libre.com, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 05/10] clk: mediatek: mt8173: Drop flags for
main/sys/univpll fixed factors
On Mon, Oct 24, 2022 at 3:23 AM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> The main/sys/univpll clocks are used as clock sources for multiple
> peripherals of different kind, some of which are critical (like AXIs);
> a rate change on any of these two will produce a rate change on many
> devices and that's likely to produce system instability if not done
> correctly: this is the reason why we have (a lot of) "fixed factor"
> main/sys/univpll divider clocks, used by MUX clocks to provide
> different rates based on PLL output dividers.
>
> Following what was done on clk-mt8186-topckgen and also preventing the
> same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned
> clocks.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
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