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Message-ID: <20221025065214.4663-6-thippeswamy.havalige@amd.com>
Date: Tue, 25 Oct 2022 12:22:06 +0530
From: Thippeswamy Havalige <thippeswamy.havalige@....com>
To: <linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>, <krzysztof.kozlowski@...aro.org>
CC: <bhelgaas@...gle.com>, <michals@...inx.com>, <robh+dt@...nel.org>,
<lorenzo.pieralisi@....com>, <bharat.kumar.gogada@....com>,
"Thippeswamy Havalige" <thippeswamy.havalige@....com>
Subject: [PATCH 05/13] microblaze/PCI: Remove unused device tree parsing for a host bridge resources
Remove unused pci_process_bridge_OF_ranges function, used to
parse the "ranges" property of a PCI host device.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
---
arch/microblaze/include/asm/pci-bridge.h | 13 ---
arch/microblaze/pci/pci-common.c | 163 -------------------------------
arch/microblaze/pci/xilinx_pci.c | 5 -
3 files changed, 181 deletions(-)
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index ce74b0c..252bcc1 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -38,20 +38,11 @@ struct pci_controller {
void __iomem *io_base_virt;
resource_size_t io_base_phys;
- resource_size_t pci_io_size;
-
/* Some machines (PReP) have a non 1:1 mapping of
* the PCI memory space in the CPU bus space
*/
resource_size_t pci_mem_offset;
- /* Some machines have a special region to forward the ISA
- * "memory" cycles such as VGA memory regions. Left to 0
- * if unsupported
- */
- resource_size_t isa_mem_phys;
- resource_size_t isa_mem_size;
-
struct pci_ops *ops;
unsigned int __iomem *cfg_addr;
void __iomem *cfg_data;
@@ -107,10 +98,6 @@ extern void setup_indirect_pci(struct pci_controller *hose,
resource_size_t cfg_addr,
resource_size_t cfg_data, u32 flags);
-/* Fill up host controller resources from the OF node */
-extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
- struct device_node *dev, int primary);
-
/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index ef4a9fc..12764df0 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -171,169 +171,6 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
*end = rsrc->end;
}
-/**
- * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
- * @hose: newly allocated pci_controller to be setup
- * @dev: device node of the host bridge
- * @primary: set if primary bus (32 bits only, soon to be deprecated)
- *
- * This function will parse the "ranges" property of a PCI host bridge device
- * node and setup the resource mapping of a pci controller based on its
- * content.
- *
- * Life would be boring if it wasn't for a few issues that we have to deal
- * with here:
- *
- * - We can only cope with one IO space range and up to 3 Memory space
- * ranges. However, some machines (thanks Apple !) tend to split their
- * space into lots of small contiguous ranges. So we have to coalesce.
- *
- * - We can only cope with all memory ranges having the same offset
- * between CPU addresses and PCI addresses. Unfortunately, some bridges
- * are setup for a large 1:1 mapping along with a small "window" which
- * maps PCI address 0 to some arbitrary high address of the CPU space in
- * order to give access to the ISA memory hole.
- * The way out of here that I've chosen for now is to always set the
- * offset based on the first resource found, then override it if we
- * have a different offset and the previous was set by an ISA hole.
- *
- * - Some busses have IO space not starting at 0, which causes trouble with
- * the way we do our IO resource renumbering. The code somewhat deals with
- * it for 64 bits but I would expect problems on 32 bits.
- *
- * - Some 32 bits platforms such as 4xx can have physical space larger than
- * 32 bits so we need to use 64 bits values for the parsing
- */
-void pci_process_bridge_OF_ranges(struct pci_controller *hose,
- struct device_node *dev, int primary)
-{
- int memno = 0, isa_hole = -1;
- unsigned long long isa_mb = 0;
- struct resource *res;
- struct of_pci_range range;
- struct of_pci_range_parser parser;
-
- pr_info("PCI host bridge %pOF %s ranges:\n",
- dev, primary ? "(primary)" : "");
-
- /* Check for ranges property */
- if (of_pci_range_parser_init(&parser, dev))
- return;
-
- pr_debug("Parsing ranges property...\n");
- for_each_of_pci_range(&parser, &range) {
- /* Read next ranges element */
-
- /* If we failed translation or got a zero-sized region
- * (some FW try to feed us with non sensical zero sized regions
- * such as power3 which look like some kind of attempt
- * at exposing the VGA memory hole)
- */
- if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
- continue;
-
- /* Act based on address space type */
- res = NULL;
- switch (range.flags & IORESOURCE_TYPE_BITS) {
- case IORESOURCE_IO:
- pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
- range.cpu_addr, range.cpu_addr + range.size - 1,
- range.pci_addr);
-
- /* We support only one IO range */
- if (hose->pci_io_size) {
- pr_info(" \\--> Skipped (too many) !\n");
- continue;
- }
- /* On 32 bits, limit I/O space to 16MB */
- if (range.size > 0x01000000)
- range.size = 0x01000000;
-
- /* 32 bits needs to map IOs here */
- hose->io_base_virt = ioremap(range.cpu_addr,
- range.size);
-
- /* Expect trouble if pci_addr is not 0 */
- if (primary)
- isa_io_base =
- (unsigned long)hose->io_base_virt;
- /* pci_io_size and io_base_phys always represent IO
- * space starting at 0 so we factor in pci_addr
- */
- hose->pci_io_size = range.pci_addr + range.size;
- hose->io_base_phys = range.cpu_addr - range.pci_addr;
-
- /* Build resource */
- res = &hose->io_resource;
- range.cpu_addr = range.pci_addr;
-
- break;
- case IORESOURCE_MEM:
- pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
- range.cpu_addr, range.cpu_addr + range.size - 1,
- range.pci_addr,
- (range.flags & IORESOURCE_PREFETCH) ?
- "Prefetch" : "");
-
- /* We support only 3 memory ranges */
- if (memno >= 3) {
- pr_info(" \\--> Skipped (too many) !\n");
- continue;
- }
- /* Handles ISA memory hole space here */
- if (range.pci_addr == 0) {
- isa_mb = range.cpu_addr;
- isa_hole = memno;
- if (primary || isa_mem_base == 0)
- isa_mem_base = range.cpu_addr;
- hose->isa_mem_phys = range.cpu_addr;
- hose->isa_mem_size = range.size;
- }
-
- /* We get the PCI/Mem offset from the first range or
- * the, current one if the offset came from an ISA
- * hole. If they don't match, bugger.
- */
- if (memno == 0 ||
- (isa_hole >= 0 && range.pci_addr != 0 &&
- hose->pci_mem_offset == isa_mb))
- hose->pci_mem_offset = range.cpu_addr -
- range.pci_addr;
- else if (range.pci_addr != 0 &&
- hose->pci_mem_offset != range.cpu_addr -
- range.pci_addr) {
- pr_info(" \\--> Skipped (offset mismatch) !\n");
- continue;
- }
-
- /* Build resource */
- res = &hose->mem_resources[memno++];
- break;
- }
- if (res != NULL) {
- res->name = dev->full_name;
- res->flags = range.flags;
- res->start = range.cpu_addr;
- res->end = range.cpu_addr + range.size - 1;
- res->parent = res->child = res->sibling = NULL;
- }
- }
-
- /* If there's an ISA hole and the pci_mem_offset is -not- matching
- * the ISA hole offset, then we need to remove the ISA hole from
- * the resource list for that brige
- */
- if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
- unsigned int next = isa_hole + 1;
- pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
- if (next < memno)
- memmove(&hose->mem_resources[isa_hole],
- &hose->mem_resources[next],
- sizeof(struct resource) * (memno - next));
- hose->mem_resources[--memno].flags = 0;
- }
-}
-
/* Display the domain number in /proc */
int pci_proc_domain(struct pci_bus *bus)
{
diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c
index 7ed6647..f1a5112 100644
--- a/arch/microblaze/pci/xilinx_pci.c
+++ b/arch/microblaze/pci/xilinx_pci.c
@@ -114,9 +114,4 @@ void __init xilinx_pci_init(void)
out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
iounmap(pci_reg);
- /* Register the host bridge with the linux kernel! */
- pci_process_bridge_OF_ranges(hose, pci_node,
- INDIRECT_TYPE_SET_CFG_TYPE);
-
- pr_info("xilinx-pci: Registered PCI host bridge\n");
}
--
1.8.3.1
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