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Message-ID: <20221025090306.297886-14-tudor.ambarus@microchip.com>
Date: Tue, 25 Oct 2022 12:02:47 +0300
From: Tudor Ambarus <tudor.ambarus@...rochip.com>
To: <vkoul@...nel.org>, <peda@...ntia.se>, <du@...ntia.se>
CC: <maciej.sosnowski@...el.com>, <nicolas.ferre@...rochip.com>,
<mripard@...nel.org>, <torfl6749@...il.com>,
<linux-kernel@...r.kernel.org>, <dmaengine@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
"Tudor Ambarus" <tudor.ambarus@...rochip.com>,
<stable@...r.kernel.org>
Subject: [PATCH v2 13/32] dmaengine: at_hdmac: Don't allow CPU to reorder channel enable
at_hdmac uses __raw_writel for register writes. In the absence of a
barrier, the CPU may reorder the register operations.
Introduce a write memory barrier so that the CPU does not reorder the
channel enable, thus the start of the transfer, without making sure that
all the pre-required register fields are already written.
Fixes: dc78baa2b90b ("dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller")
Reported-by: Peter Rosin <peda@...ntia.se>
Signed-off-by: Tudor Ambarus <tudor.ambarus@...rochip.com>
Cc: stable@...r.kernel.org
Link: https://lore.kernel.org/lkml/13c6c9a2-6db5-c3bf-349b-4c127ad3496a@axentia.se/
---
drivers/dma/at_hdmac.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 80eeb4fb88ef..968a5aba47cd 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -256,6 +256,8 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
ATC_SPIP_BOUNDARY(first->boundary));
channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) |
ATC_DPIP_BOUNDARY(first->boundary));
+ /* Don't allow CPU to reorder channel enable. */
+ wmb();
dma_writel(atdma, CHER, atchan->mask);
vdbg_dump_regs(atchan);
--
2.25.1
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