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Message-Id: <20221025132953.81286-4-linux@fw-web.de>
Date: Tue, 25 Oct 2022 15:29:50 +0200
From: Frank Wunderlich <linux@...web.de>
To: linux-mediatek@...ts.infradead.org
Cc: Frank Wunderlich <frank-w@...lic-files.de>,
Chaotian Jing <chaotian.jing@...iatek.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Wenbin Mei <wenbin.mei@...iatek.com>,
linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Sam Shih <Sam.Shih@...iatek.com>
Subject: [PATCH v5 3/6] arm64: dts: mediatek: mt2712e: swap last 2 clocks to match binding
From: Frank Wunderlich <frank-w@...lic-files.de>
First 3 clocks for mt2712 need to be "source", "hclk", "source_cg"
so swap last 2 of mmc0 to match the binding.
Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e6d7453e56e0..9dc0794fcd2e 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -766,9 +766,9 @@ mmc0: mmc@...30000 {
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0>,
<&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
- <&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
- <&pericfg CLK_PERI_MSDC50_0_EN>;
- clock-names = "source", "hclk", "bus_clk", "source_cg";
+ <&pericfg CLK_PERI_MSDC50_0_EN>,
+ <&pericfg CLK_PERI_MSDC30_0_QTR_EN>;
+ clock-names = "source", "hclk", "source_cg", "bus_clk";
status = "disabled";
};
--
2.34.1
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