linux-kernel - RE: [PATCH 1/2] x86/hyperv: fix invalid writes to MSRs during root partition kexec

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Message-ID: <BYAPR21MB168837A9E4B73D7B26040B52D7309@BYAPR21MB1688.namprd21.prod.outlook.com>
Date:   Wed, 26 Oct 2022 14:58:16 +0000
From:   "Michael Kelley (LINUX)" <mikelley@...rosoft.com>
To:     Anirudh Rayabharam <anrayabh@...ux.microsoft.com>,
        KY Srinivasan <kys@...rosoft.com>,
        Haiyang Zhang <haiyangz@...rosoft.com>,
        Stephen Hemminger <sthemmin@...rosoft.com>,
        "wei.liu@...nel.org" <wei.liu@...nel.org>,
        Dexuan Cui <decui@...rosoft.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "x86@...nel.org" <x86@...nel.org>, "hpa@...or.com" <hpa@...or.com>,
        "daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
        Arnd Bergmann <arnd@...db.de>,
        "linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>
CC:     "kumarpraveen@...ux.microsoft.com" <kumarpraveen@...ux.microsoft.com>,
        "mail@...rudhrb.com" <mail@...rudhrb.com>
Subject: RE: [PATCH 1/2] x86/hyperv: fix invalid writes to MSRs during root
 partition kexec

From: Anirudh Rayabharam <anrayabh@...ux.microsoft.com> Sent: Wednesday, October 26, 2022 6:47 AM
> 
> hv_cleanup resets the hypercall page by setting the MSR to 0. However,
> the root partition is not allowed to write to the GPA bits of the MSR.
> Instead, it uses the hypercall page provided by the MSR. Similar is the
> case with the reference TSC MSR.
> 
> Clear only the enable bit instead of zeroing the entire MSR to make
> the code valid for root partition too.

When the enable bit is cleared (but not the PFN) in the MSR, do we know
for sure that Hyper-V removes the overlay page for the PFN?  Making sure
that the overlay page is removed is the main reason for clearing the entire
MSR.   If we're going to leave the PFN in place and just clear the enable bit,
we need to confirm with the Hyper-V guys that the overlay page will be
removed.

Michael

> 
> Signed-off-by: Anirudh Rayabharam <anrayabh@...ux.microsoft.com>
> ---
>  arch/x86/hyperv/hv_init.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
> index 29774126e931..76ff63d69461 100644
> --- a/arch/x86/hyperv/hv_init.c
> +++ b/arch/x86/hyperv/hv_init.c
> @@ -537,6 +537,7 @@ void __init hyperv_init(void)
>  void hyperv_cleanup(void)
>  {
>  	union hv_x64_msr_hypercall_contents hypercall_msr;
> +	u64 tsc_msr;
> 
>  	unregister_syscore_ops(&hv_syscore_ops);
> 
> @@ -552,12 +553,14 @@ void hyperv_cleanup(void)
>  	hv_hypercall_pg = NULL;
> 
>  	/* Reset the hypercall page */
> -	hypercall_msr.as_uint64 = 0;
> +	rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
> +	hypercall_msr.enable = 0;
>  	wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
> 
>  	/* Reset the TSC page */
> -	hypercall_msr.as_uint64 = 0;
> -	wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64);
> +	rdmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr);
> +	tsc_msr &= ~BIT_ULL(0);
> +	wrmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr);
>  }
> 
>  void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die)
> --
> 2.34.1