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Message-ID: <CAPY8ntDvg4Ei-b=adWHi5A8BKamd53Q3FnoyOXvW5zeuYyLArg@mail.gmail.com>
Date: Wed, 26 Oct 2022 17:09:31 +0100
From: Dave Stevenson <dave.stevenson@...pberrypi.com>
To: maxime@...no.tech
Cc: Daniel Vetter <daniel@...ll.ch>, Emma Anholt <emma@...olt.net>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Maxime Ripard <mripard@...nel.org>,
Ray Jui <rjui@...adcom.com>,
Florian Fainelli <f.fainelli@...il.com>,
David Airlie <airlied@...ux.ie>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>,
Scott Branden <sbranden@...adcom.com>,
Stefan Wahren <stefan.wahren@...e.com>,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
Dom Cobley <popcornmix@...il.com>, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rpi-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 7/7] drm/vc4: Make sure we don't end up with a core
clock too high
On Thu, 20 Oct 2022 at 10:14, <maxime@...no.tech> wrote:
>
> Following the clock rate range improvements to the clock framework,
> trying to set a disjoint range on a clock will now result in an error.
>
> Thus, we can't set a minimum rate higher than the maximum reported by
> the firmware, or clk_set_min_rate() will fail.
>
> Thus we need to clamp the rate we are about to ask for to the maximum
> rate possible on that clock.
>
> Signed-off-by: Maxime Ripard <maxime@...no.tech>
Thanks Maxime.
Reviewed-by: Dave Stevenson <dave.stevenson@...pberrypi.com>
> ---
> drivers/gpu/drm/vc4/vc4_kms.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
> index 4419e810103d..5c97642ed66a 100644
> --- a/drivers/gpu/drm/vc4/vc4_kms.c
> +++ b/drivers/gpu/drm/vc4/vc4_kms.c
> @@ -396,8 +396,8 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
> if (vc4->is_vc5) {
> unsigned long state_rate = max(old_hvs_state->core_clock_rate,
> new_hvs_state->core_clock_rate);
> - unsigned long core_rate = max_t(unsigned long,
> - 500000000, state_rate);
> + unsigned long core_rate = clamp_t(unsigned long, state_rate,
> + 500000000, hvs->max_core_rate);
>
> drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate);
>
> @@ -431,14 +431,17 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
> drm_atomic_helper_cleanup_planes(dev, state);
>
> if (vc4->is_vc5) {
> - drm_dbg(dev, "Running the core clock at %lu Hz\n",
> - new_hvs_state->core_clock_rate);
> + unsigned long core_rate = min_t(unsigned long,
> + hvs->max_core_rate,
> + new_hvs_state->core_clock_rate);
> +
> + drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate);
>
> /*
> * Request a clock rate based on the current HVS
> * requirements.
> */
> - WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate));
> + WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
>
> drm_dbg(dev, "Core clock actual rate: %lu Hz\n",
> clk_get_rate(hvs->core_clk));
>
> --
> b4 0.10.1
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