linux-kernel - Re: [PATCH 3/5] ACPI/PCI: Add AER bits #defines for PCIE/PCI-X bridges

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20221027215644.GA844326@bhelgaas>
Date:   Thu, 27 Oct 2022 16:56:44 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     LeoLiu-oc <LeoLiu-oc@...oxin.com>
Cc:     rafael@...nel.org, lenb@...nel.org, james.morse@....com,
        tony.luck@...el.com, bp@...en8.de, robert.moore@...el.com,
        ying.huang@...el.com, rdunlap@...radead.org, bhelgaas@...gle.com,
        linux-acpi@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, devel@...ica.org,
        CobeChen@...oxin.com, TonyWWang@...oxin.com, ErosZhang@...oxin.com
Subject: Re: [PATCH 3/5] ACPI/PCI: Add AER bits #defines for PCIE/PCI-X
 bridges

On Thu, Oct 27, 2022 at 11:15:54AM +0800, LeoLiu-oc wrote:
> From: leoliu-oc <leoliu-oc@...oxin.com>
> 
> Define PCI Express Advanced Error Reporting Extended Capabilities bits.
> 
> Signed-off-by: leoliu-oc <leoliu-oc@...oxin.com>
> ---
>  include/uapi/linux/pci_regs.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..3662106fd8dc 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -799,6 +799,11 @@
>  #define  PCI_ERR_ROOT_AER_IRQ		0xf8000000 /* Advanced Error Interrupt Message Number */
>  #define PCI_ERR_ROOT_ERR_SRC	0x34	/* Error Source Identification */
>  
> +/* PCI Express Advanced Error Reporting Extended Capabilities for Bridges */
> +#define PCI_ERR_UNCOR_MASK2		0x30	/* Secondary Uncorrectable Error Mask */
> +#define PCI_ERR_UNCOR_SEVER2	0x34	/* Secondary Uncorrectable Error Severit */
> +#define PCI_ERR_CAP2			0x38	/* Secondary Advanced Error Capabilities */

Can you include a spec reference for these?  I'm looking at PCIe r6.0,
sec 7.8.4, and I don't see anything I can match up with these.

Bjorn