| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20221027123432.1818530-3-robert.foss@linaro.org>
Date: Thu, 27 Oct 2022 14:34:30 +0200
From: Robert Foss <robert.foss@...aro.org>
To: agross@...nel.org, bjorn.andersson@...aro.org,
konrad.dybcio@...ainline.org, mturquette@...libre.com,
sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Bjorn Andersson <quic_bjorande@...cinc.com>,
dmitry.baryshkov@...aro.org, Jonathan Marek <jonathan@...ek.ca>
Cc: Robert Foss <robert.foss@...aro.org>
Subject: [PATCH v1 3/5] dt-bindings: clock: dispcc-sm8250: Add EDP_LINK_DIV_CLK_SRC index
Add this previously missing index, since it is supported by the SoCs
targeted by the dispcc-sm8250 driver.
Signed-off-by: Robert Foss <robert.foss@...aro.org>
---
include/dt-bindings/clock/qcom,dispcc-sm8250.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
index ce001cbbc27f..767fdb27e514 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sm8250.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -64,6 +64,7 @@
#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54
#define DISP_CC_MDSS_EDP_PIXEL_CLK 55
#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56
+#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 57
/* DISP_CC Reset */
#define DISP_CC_MDSS_CORE_BCR 0
--
2.34.1
Powered by blists - more mailing lists