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Message-Id: <20221028165921.94487-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date:   Fri, 28 Oct 2022 17:59:17 +0100
From:   Prabhakar <prabhakar.csengg@...il.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Guo Ren <guoren@...nel.org>, Anup Patel <anup@...infault.org>,
        Atish Patra <atishp@...osinc.com>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        Prabhakar <prabhakar.csengg@...il.com>,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
---
v4 -> v5
* Sorted as per SoC name
* Included RB tag from Conor

v3 -> v4
* Dropped SOC_RENESAS_RZFIVE config option
* Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
  under ARCH_RENESAS
* Updated commit message
* Dropped RB tag
* Used riscv instead of RISC-V in subject line

v2 -> v3
* Included RB tag from Geert

v1 -> v2
* No Change
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..75fb0390d6bd 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE
 	help
 	  This enables support for Microchip PolarFire SoC platforms.
 
+config ARCH_RENESAS
+	bool "Renesas RISC-V SoCs"
+	help
+	  This enables support for the RISC-V based Renesas SoCs.
+
 config SOC_SIFIVE
 	bool "SiFive SoCs"
 	select SERIAL_SIFIVE if TTY
-- 
2.25.1

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