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Message-Id: <166699579458.30369.3811976740296212930.b4-ty@rivosinc.com>
Date:   Fri, 28 Oct 2022 15:23:14 -0700
From:   Palmer Dabbelt <palmer@...osinc.com>
To:     guoren@...nel.org, akpm@...ux-foundation.org,
        alexandre.ghiti@...onical.com, anup@...infault.org,
        Jinyu Tang <tjytimi@....com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        tongtiangen@...wei.com, ajones@...tanamicro.com,
        Paul Walmsley <paul.walmsley@...ive.com>,
        aou@...s.berkeley.edu, panqinglin2020@...as.ac.cn,
        maobibo@...ngson.cn
Cc:     falcon@...ylab.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] riscv: support update_mmu_tlb()

On Sun, 9 Oct 2022 21:45:03 +0800, Jinyu Tang wrote:
> Add macro definition to support update_mmu_tlb() for riscv,
> this function is from commit:7df676974359 ("mm/memory.c:Update
> local TLB if PTE entry exists").
> 
> update_mmu_tlb() is used when a thread notice that other cpu thread
> has handled the fault and changed the PTE. For MIPS, it's worth to
> do that,this cpu thread will trap in tlb fault again otherwise.
> 
> [...]

Applied, thanks!

[1/1] riscv: support update_mmu_tlb()
      https://git.kernel.org/palmer/c/1b52861f0e04

Best regards,
-- 
Palmer Dabbelt <palmer@...osinc.com>

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