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Date: Fri, 28 Oct 2022 12:40:50 +0100 From: "Lad, Prabhakar" <prabhakar.csengg@...il.com> To: Geert Uytterhoeven <geert@...ux-m68k.org> Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>, Conor Dooley <conor.dooley@...rochip.com>, Samuel Holland <samuel@...lland.org>, soc@...nel.org, linux-arm-kernel@...ts.infradead.org, linux-riscv@...ts.infradead.org, linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> Subject: Re: [PATCH v2 2/2] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Hi Geert, Thank you for the review. On Fri, Oct 28, 2022 at 12:35 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, Oct 26, 2022 at 12:06 AM Prabhakar <prabhakar.csengg@...il.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> > > > > Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi > > can be shared with RZ/Five (RISC-V SoC). > > > > Below are the changes due to which SoC specific parts are moved to > > r9a07g043u.dtsi: > > - RZ/G2UL has Cortex-A55 (ARM64) whereas the RZ/Five has AX45MP (RISC-V) > > - RZ/G2UL has GICv3 as interrupt controller whereas the RZ/Five has PLIC > > - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing > > for SYSC block on RZ/Five > > - RZ/G2UL has armv8-timer whereas the RZ/Five has riscv-timer > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be> > i.e. will queue in renesas-devel for v6.2. > > > --- > > RFC->v2 > > * Updated commit message about timer > > Right. And I'll add while applying: > > - RZ/G2UL has PSCI whereas RZ/Five have OpenSBI > That makes sense, thanks. Cheers, Prabhakar
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