linux-kernel - Re: [PATCH 16/20] phy: qcom-qmp-pcie: drop start-ctrl abstraction

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Message-ID: <Y1vJw2Co5tVhUrc+@matsya>
Date:   Fri, 28 Oct 2022 17:53:31 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, mani@...nel.org
Cc:     Johan Hovold <johan+linaro@...nel.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 16/20] phy: qcom-qmp-pcie: drop start-ctrl abstraction

On 13-10-22, 00:20, Dmitry Baryshkov wrote:
> On 12/10/2022 11:49, Johan Hovold wrote:
> > All PCIe PHYs need to start and stop the SerDes and PCS so drop the
> > start-ctrl abstraction which is no longer needed since the QMP driver
> > split.
> > 
> > Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
> > ---
> >   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 +++---------------
> >   1 file changed, 3 insertions(+), 15 deletions(-)
> 
> I think it should be possible to also drop the pwrdn_ctrl by replacing it
> with something like no_refclk_drv_dsbl. However I'd like to understand why
> this is not required for SDX55. Is this the peculiarity of that platform? Or
> is it a specifics of the EP mode?
> Many, Vinod, do you know the answer by chance?

Adding Mani, i am not sure maybe sdx55 specific...?

> 
> Nevertheless, for this patch:
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> 
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > index d3e7e673114f..5534a4ad0243 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > @@ -1355,7 +1355,6 @@ struct qmp_phy_cfg {
> >   	/* array of registers with different offsets */
> >   	const unsigned int *regs;
> > -	unsigned int start_ctrl;
> >   	unsigned int pwrdn_ctrl;
> >   	/* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
> >   	unsigned int phy_status;
> > @@ -1491,7 +1490,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> >   	.num_vregs		= 0,
> >   	.regs			= pciephy_regs_layout,
> > -	.start_ctrl		= SERDES_START | PCS_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1517,7 +1515,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
> >   	.num_vregs		= 0,
> >   	.regs			= ipq_pciephy_gen3_regs_layout,
> > -	.start_ctrl		= SERDES_START | PCS_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> > @@ -1547,7 +1544,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
> >   	.num_vregs		= 0,
> >   	.regs			= ipq_pciephy_gen3_regs_layout,
> > -	.start_ctrl		= SERDES_START | PCS_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1575,7 +1571,6 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sdm845_qmp_pciephy_regs_layout,
> > -	.start_ctrl		= PCS_START | SERDES_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1601,7 +1596,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sdm845_qhp_pciephy_regs_layout,
> > -	.start_ctrl		= PCS_START | SERDES_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1639,7 +1633,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sm8250_pcie_regs_layout,
> > -	.start_ctrl		= PCS_START | SERDES_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1677,7 +1670,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sm8250_pcie_regs_layout,
> > -	.start_ctrl		= PCS_START | SERDES_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1703,7 +1695,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= pciephy_regs_layout,
> > -	.start_ctrl             = SERDES_START | PCS_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> > @@ -1733,7 +1724,6 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sm8250_pcie_regs_layout,
> > -	.start_ctrl		= PCS_START | SERDES_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1761,7 +1751,6 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sm8250_pcie_regs_layout,
> > -	.start_ctrl		= PCS_START | SERDES_START,
> >   	.pwrdn_ctrl		= SW_PWRDN,
> >   	.phy_status		= PHYSTATUS_4_20,
> >   };
> > @@ -1789,7 +1778,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sm8250_pcie_regs_layout,
> > -	.start_ctrl             = SERDES_START | PCS_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS,
> >   };
> > @@ -1832,7 +1820,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> >   	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> >   	.regs			= sm8250_pcie_regs_layout,
> > -	.start_ctrl             = SERDES_START | PCS_START,
> >   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> >   	.phy_status		= PHYSTATUS_4_20,
> >   };
> > @@ -1997,7 +1984,7 @@ static int qmp_pcie_power_on(struct phy *phy)
> >   	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> >   	/* start SerDes and Phy-Coding-Sublayer */
> > -	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> > +	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
> >   	if (!cfg->skip_start_delay)
> >   		usleep_range(1000, 1200);
> > @@ -2030,7 +2017,8 @@ static int qmp_pcie_power_off(struct phy *phy)
> >   	qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> >   	/* stop SerDes and Phy-Coding-Sublayer */
> > -	qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> > +	qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL],
> > +			SERDES_START | PCS_START);
> >   	/* Put PHY into POWER DOWN state: active low */
> >   	qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> 
> -- 
> With best wishes
> Dmitry

-- 
~Vinod