linux-kernel - RE: [PATCH 3/5] cxl/pci: Discover and cache pointer to RCD dport's CXL RAS registers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <MN2PR11MB3645BDC3B58C198BDB9B7B0888329@MN2PR11MB3645.namprd11.prod.outlook.com>
Date:   Fri, 28 Oct 2022 12:53:10 +0000
From:   <Ariel.Sibley@...rochip.com>
To:     <terry.bowman@....com>, <alison.schofield@...el.com>,
        <vishal.l.verma@...el.com>, <dave.jiang@...el.com>,
        <ira.weiny@...el.com>, <bwidawsk@...nel.org>,
        <dan.j.williams@...el.com>
CC:     <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <bhelgaas@...gle.com>, <rafael@...nel.org>, <lenb@...nel.org>,
        <Jonathan.Cameron@...wei.com>, <dave@...olabs.net>,
        <rrichter@....com>
Subject: RE: [PATCH 3/5] cxl/pci: Discover and cache pointer to RCD dport's
 CXL RAS registers

> -----Original Message-----
> From: Terry Bowman <terry.bowman@....com>
> Sent: Friday, October 21, 2022 3:56 PM
> To: alison.schofield@...el.com; vishal.l.verma@...el.com; dave.jiang@...el.com; ira.weiny@...el.com;
> bwidawsk@...nel.org; dan.j.williams@...el.com
> Cc: terry.bowman@....com; linux-cxl@...r.kernel.org; linux-kernel@...r.kernel.org; bhelgaas@...gle.com;
> rafael@...nel.org; lenb@...nel.org; Jonathan.Cameron@...wei.com; dave@...olabs.net; rrichter@....com
> Subject: [PATCH 3/5] cxl/pci: Discover and cache pointer to RCD dport's CXL RAS registers
> 
> CXL RAS information resides in a RAS capability structure located in
> CXL.cache and CXL.mem registers.[1] The RAS capability provides CXL
> specific error information that can be helpful in debugging. This
> information is not currently logged but needs to be logged during PCIe AER
> error handling.
> 
> Update the CXL driver to find and cache a pointer to the CXL RAS
> capability. The RAS registers resides in the downport's component register
> block. Note:RAS registers are not in the upport. The component registers
> can be found by first using the RCRB to goto the downport. Next, the
> downport's 64-bit BAR[0] will point to the component register block.

I realize this patch is for dport only, but regarding "Note:RAS registers
are not in the upport.", the upstream port also has RAS registers.

Per CXL 3.0 Section 12.2.1.2 RCD Upstream Port-detected Errors:
"1. If a CXL.cache or CXL.mem logic block in UPZ detects a protocol or link
error, the block shall log the error in the CXL RAS Capability (see Section
8.2.4.16)."