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Message-ID: <20221028145901.q4i73vwagny36xdj@pengutronix.de>
Date: Fri, 28 Oct 2022 16:59:01 +0200
From: Marco Felsch <m.felsch@...gutronix.de>
To: "Peng Fan (OSS)" <peng.fan@....nxp.com>
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
shawnguo@...nel.org, s.hauer@...gutronix.de,
devicetree@...r.kernel.org, Peng Fan <peng.fan@....com>,
linux-kernel@...r.kernel.org, linux-imx@....com,
kernel@...gutronix.de, festevam@...il.com,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH V2 02/15] arm64: dts: imx8mp-evk: correct pcie pad
settings
On 22-10-24, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@....com>
>
> According to RM bit layout, BIT3 and BIT0 are reserved.
> 8 7 6 5 4 3 2 1 0
> PE HYS PUE ODE FSEL X DSE X
>
> Although function is not broken, we should not set reserved bit.
>
> Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support")
> Signed-off-by: Peng Fan <peng.fan@....com>
LGTM, feel free to add my:
Reviewed-by: Marco Felsch <m.felsch@...gutronix.de>
> ---
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 9f1469db554d..b4c1ef2559f2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -544,14 +544,14 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>
> pinctrl_pcie0: pcie0grp {
> fsl,pins = <
> - MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
> - MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
> + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
> + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
> >;
> };
>
> pinctrl_pcie0_reg: pcie0reggrp {
> fsl,pins = <
> - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
> + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
> >;
> };
>
> --
> 2.37.1
>
>
>
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