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Date: Sat, 29 Oct 2022 14:27:50 +0800
From: Yinbo Zhu <zhuyinbo@...ngson.cn>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Huacai Chen <chenhuacai@...nel.org>,
WANG Xuerui <kernel@...0n.name>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
Jianmin Lv <lvjianmin@...ngson.cn>,
Yang Li <yang.lee@...ux.alibaba.com>,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, loongarch@...ts.linux.dev
Subject: Re: [PATCH v6 2/3] clk: clk-loongson2: add clock controller driver
support
在 2022/10/28 下午7:42, Krzysztof Kozlowski 写道:
> On 28/10/2022 02:19, Yinbo Zhu wrote:
>> This driver provides support for clock controller on Loongson-2 SoC
>> , the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock
>> , there are five independent PLLs inside, each of which PLL can
>
> Same problem as in other patch - no new lines before commas.
>
>> provide up to three sets of frequency dependent clock outputs.
>>
>> Signed-off-by: Yinbo Zhu <zhuyinbo@...ngson.cn>
>> ---
>> MAINTAINERS | 1 +
>> arch/loongarch/Kconfig | 1 +
>> arch/loongarch/kernel/time.c | 3 +
>> drivers/clk/Kconfig | 9 ++
>> drivers/clk/Makefile | 1 +
>> drivers/clk/clk-loongson2.c | 285 +++++++++++++++++++++++++++++++++++
>> 6 files changed, 300 insertions(+)
>> create mode 100644 drivers/clk/clk-loongson2.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 14af7ebf2be1..5136684fb6c6 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -11911,6 +11911,7 @@ LOONGSON-2 SOC SERIES CLOCK DRIVER
>> M: Yinbo Zhu <zhuyinbo@...ngson.cn>
>> L: linux-clk@...r.kernel.org
>> S: Maintained
>> +F: drivers/clk/clk-loongson2.c
>> F: include/dt-bindings/clock/loongson,ls2k-clk.h
>>
>> LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
>> diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
>> index 26aeb1408e56..8b65f349cd6e 100644
>> --- a/arch/loongarch/Kconfig
>> +++ b/arch/loongarch/Kconfig
>> @@ -122,6 +122,7 @@ config LOONGARCH
>> select USE_PERCPU_NUMA_NODE_ID
>> select USER_STACKTRACE_SUPPORT
>> select ZONE_DMA32
>> + select COMMON_CLK
>>
>> config 32BIT
>> bool
>> diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
>> index 786735dcc8d6..09f20bc81798 100644
>> --- a/arch/loongarch/kernel/time.c
>> +++ b/arch/loongarch/kernel/time.c
>> @@ -12,6 +12,7 @@
>> #include <linux/kernel.h>
>> #include <linux/sched_clock.h>
>> #include <linux/spinlock.h>
>> +#include <linux/of_clk.h>
>>
>> #include <asm/cpu-features.h>
>> #include <asm/loongarch.h>
>> @@ -214,6 +215,8 @@ int __init constant_clocksource_init(void)
>>
>> void __init time_init(void)
>> {
>> + of_clk_init(NULL);
>> +
>> if (!cpu_has_cpucfg)
>> const_clock_freq = cpu_clock_freq;
>> else
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index 48f8f4221e21..e85a3ed88d4c 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -428,6 +428,15 @@ config COMMON_CLK_K210
>> help
>> Support for the Canaan Kendryte K210 RISC-V SoC clocks.
>>
>> +config COMMON_CLK_LOONGSON2
>
> Messed up order.
okay, I got it.
>
>> + bool "Clock driver for Loongson-2 SoC"
>> + depends on COMMON_CLK && OF
>> + help
>> + This driver provides support for Clock Controller that base on
>> + Common Clock Framework Controller (CCF) on Loongson-2 SoC. The
>> + Clock Controller can generates and supplies clock to various
>> + peripherals within the SoC.
>> +
>> source "drivers/clk/actions/Kconfig"
>> source "drivers/clk/analogbits/Kconfig"
>> source "drivers/clk/baikal-t1/Kconfig"
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index d5db170d38d2..8ccc7436052f 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -75,6 +75,7 @@ obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
>> obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
>> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
>> obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
>> +obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o
>
> Messed up order.
>
okay, I got it.
>>
>> # please keep this section sorted lexicographically by directory path name
>> obj-y += actions/
>> diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
>> new file mode 100644
>> index 000000000000..359fede40112
>> --- /dev/null
>> +++ b/drivers/clk/clk-loongson2.c
>> @@ -0,0 +1,285 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Author: Yinbo Zhu <zhuyinbo@...ngson.cn>
>> + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
>> + */
>> +
>> +#include <linux/clkdev.h>
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <dt-bindings/clock/loongson,ls2k-clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/slab.h>
>> +#include <linux/clk.h>
>> +
>> +#define LOONGSON2_PLL_MULT_SHIFT 32
>> +#define LOONGSON2_PLL_MULT_WIDTH 10
>> +#define LOONGSON2_PLL_DIV_SHIFT 26
>> +#define LOONGSON2_PLL_DIV_WIDTH 6
>> +#define LOONGSON2_APB_FREQSCALE_SHIFT 20
>> +#define LOONGSON2_APB_FREQSCALE_WIDTH 3
>> +#define LOONGSON2_USB_FREQSCALE_SHIFT 16
>> +#define LOONGSON2_USB_FREQSCALE_WIDTH 3
>> +#define LOONGSON2_SATA_FREQSCALE_SHIFT 12
>> +#define LOONGSON2_SATA_FREQSCALE_WIDTH 3
>> +
>> +void __iomem *loongson2_pll_base;
>
> This must be static.
okay, I will add it.
>
>> +static DEFINE_SPINLOCK(loongson2_clk_lock);
>> +static struct clk_hw **hws;
>> +static struct clk_hw_onecell_data *clk_hw_data;
>
> You have way too many file-scope variables. I would expect 0 and this
> being a driver.
okay, I will move it in probe.
>
> Best regards,
> Krzysztof
>
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