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Date: Sun, 30 Oct 2022 23:01:40 +0000 From: "Lad, Prabhakar" <prabhakar.csengg@...il.com> To: Conor Dooley <conor@...nel.org> Cc: Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Geert Uytterhoeven <geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Heiko Stuebner <heiko@...ech.de>, Conor Dooley <conor.dooley@...rochip.com>, Guo Ren <guoren@...nel.org>, Anup Patel <anup@...infault.org>, Atish Patra <atishp@...osinc.com>, Heinrich Schuchardt <heinrich.schuchardt@...onical.com>, devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> Subject: Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Hi Conor, On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@...nel.org> wrote: > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote: > > Hi Conor, > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@...nel.org> wrote: > > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> > > > > > > > > Hi All, > > > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > > > entry-class social infrastructure gateway control and industrial gateway > > > > control. > > > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > - AX45MP CPU > > > > - CPG > > > > - PINCTRL > > > > > > Hey, > > > Looks like you've got a pair of warnings here from dtbs_check. I tested > > > this on top of 20221028's next, with the three branches below merged in, > > > hopefully my merges aren't the source of them: > > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@...30000: 'interrupt-controller' is a required property > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@...30000: '#interrupt-cells' is a required property > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > > Thanks for the review and test. The warnings above are coming from [0] > > as support for IRQC is missing, once that is added the warnings should > > go away. > > Right. I merged in the stuff in Geert's trees & I don't think I saw any > pending patches in the cover that I missed. Is there something else that > adds the support that's not going to make v6.2? I got rid of all the > dtbs_check warnings for v6.1 and I'd really like to keep things that > way! > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the cover letter. I'll make sure I get it posted asap and merged for v6.2. Cheers, Prabhakar
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