linux-kernel - Re: [PATCH 02/20] arm64: dts: Update cache properties for amlogic

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Message-ID: <CAFBinCBi_xT-pgdMSROHyZUfyZZE33S2YXczr9ijE52AfQVYHQ@mail.gmail.com>
Date:   Mon, 31 Oct 2022 22:09:26 +0100
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     Pierre Gondois <pierre.gondois@....com>
Cc:     neil.armstrong@...aro.org, linux-kernel@...r.kernel.org,
        Rob.Herring@....com, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Kevin Hilman <khilman@...libre.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-amlogic@...ts.infradead.org
Subject: Re: [PATCH 02/20] arm64: dts: Update cache properties for amlogic

Hi Pierre,

On Mon, Oct 31, 2022 at 2:33 PM Pierre Gondois <pierre.gondois@....com> wrote:
[...]
> To avoid cc-ing people to DTs they are not related, the get_maintainers.pl
> script was run on each patch individually. The cover-letter is at:
> https://lore.kernel.org/all/20221031091848.530938-1-pierre.gondois@arm.com/
I think Neil's question is the same as mine: is there a dt-bindings
(yaml schema) change for this as well? The idea is to alert people (or
let bots alert people) in future when adding a cache to a .dts{,i}
where the cache-level property is missing.

[...]
> >> Signed-off-by: Pierre Gondois <pierre.gondois@....com>
Your patch looks good to me. We already use the property on the 32-bit
Amlogic SoCs. So please add my:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>


Best regards,
Martin