linux-kernel - Re: [PATCH 01/10] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2

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Message-Id: <CNZZDUY2NAEQ.2MTXWFKUSHNA7@otso>
Date:   Mon, 31 Oct 2022 09:55:13 +0100
From:   "Luca Weiss" <luca.weiss@...rphone.com>
To:     "Marijn Suijten" <marijn.suijten@...ainline.org>,
        <phone-devel@...r.kernel.org>
Cc:     <~postmarketos/upstreaming@...ts.sr.ht>,
        "AngeloGioacchino Del Regno" 
        <angelogioacchino.delregno@...ainline.org>,
        "Konrad Dybcio" <konrad.dybcio@...ainline.org>,
        "Martin Botka" <martin.botka@...ainline.org>,
        "Jami Kettunen" <jami.kettunen@...ainline.org>,
        "Andy Gross" <agross@...nel.org>,
        "Bjorn Andersson" <andersson@...nel.org>,
        "Rob Herring" <robh+dt@...nel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        "Luca Weiss" <luca@...tu.xyz>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 01/10] arm64: dts: qcom: sm6350: Add resets for SDHCI
 1/2

On Sun Oct 30, 2022 at 8:32 AM CET, Marijn Suijten wrote:
> Make sure the SDHCI hardware is properly reset before interacting with
> it, to protect against any possibly indeterminate state left by the
> bootloader.
>
> Suggested-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
> Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>

Reviewed-by: Luca Weiss <luca.weiss@...rphone.com>
Tested-by: Luca Weiss <luca.weiss@...rphone.com> # sm7225-fairphone-fp4

Regards
Luca

> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index c39de7d3ace0..a3ae765d9781 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -490,6 +490,7 @@ sdhc_1: mmc@...000 {
>  				 <&gcc GCC_SDCC1_APPS_CLK>,
>  				 <&rpmhcc RPMH_CXO_CLK>;
>  			clock-names = "iface", "core", "xo";
> +			resets = <&gcc GCC_SDCC1_BCR>;
>  			qcom,dll-config = <0x000f642c>;
>  			qcom,ddr-config = <0x80040868>;
>  			power-domains = <&rpmhpd SM6350_CX>;
> @@ -1068,6 +1069,7 @@ sdhc_2: mmc@...4000 {
>  				 <&gcc GCC_SDCC2_APPS_CLK>,
>  				 <&rpmhcc RPMH_CXO_CLK>;
>  			clock-names = "iface", "core", "xo";
> +			resets = <&gcc GCC_SDCC2_BCR>;
>  			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
>  					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
>  			interconnect-names = "sdhc-ddr", "cpu-sdhc";
> -- 
> 2.38.1