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Message-ID: <PH0PR11MB509629C9B80D4331AAF0E5AC9B379@PH0PR11MB5096.namprd11.prod.outlook.com>
Date: Mon, 31 Oct 2022 09:24:25 +0000
From: <Tharunkumar.Pasumarthi@...rochip.com>
To: <andy.shevchenko@...il.com>, <Kumaravel.Thiagarajan@...rochip.com>
CC: <gregkh@...uxfoundation.org>, <jirislaby@...nel.org>,
<ilpo.jarvinen@...ux.intel.com>, <u.kleine-koenig@...gutronix.de>,
<johan@...nel.org>, <wander@...hat.com>,
<etremblay@...tech-controls.com>, <macro@...am.me.uk>,
<geert+renesas@...der.be>, <jk@...abs.org>,
<phil.edworthy@...esas.com>, <lukas@...ner.de>,
<linux-kernel@...r.kernel.org>, <linux-serial@...r.kernel.org>,
<UNGLinuxDriver@...rochip.com>
Subject: RE: [PATCH v2 tty-next 1/3] 8250: microchip: pci1xxxx: Add driver for
quad-uart support.
> -----Original Message-----
> From: Andy Shevchenko <andy.shevchenko@...il.com>
> Sent: Monday, October 3, 2022 2:53 PM
> To: Kumaravel Thiagarajan - I21417
> <Kumaravel.Thiagarajan@...rochip.com>
> Subject: Re: [PATCH v2 tty-next 1/3] 8250: microchip: pci1xxxx: Add driver for
> quad-uart support.
>
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> > + [PORT_MCHP16550A] = {
> > + .name = "MCHP16550A",
> > + .fifo_size = 256,
> > + .tx_loadsz = 256,
> > + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
> > + .rxtrig_bytes = {2, 66, 130, 194},
> > + .flags = UART_CAP_FIFO,
> > + },
>
> Can you assign this in ->setup() or so instead of adding a new port type?
Hi Andy,
If I understand correctly, you suggest doing something like this inside pci1xxxx_setup() API:
pci1xxxx_setup(.., uart_8250_port *port, ..) {
..
port->port.fifosize = 256;
port->tx_loadsz = 256;
port->capabilities = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01;
..
}
instead of adding new port type PORT_MCHP16550A. But, if I do this, I cannot use sysfs interface for updating rx_trig_bytes right?
Kindly correct me if my understanding is wrong.
Thanks,
Tharun Kumar P
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